FinFET Strained Material Gradient Doping

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Solution Overview

Problem

The challenge in fabricating FinFETs lies in achieving efficient electrical control and reduced resistance in the conducting channel, which is not adequately addressed by conventional methods, particularly in scaling down semiconductor devices.

Innovation Solution

The method involves patterning a semiconductor substrate to form trenches and fins, forming insulators and a gate stack, and growing a strained material with a bulk layer having a gradient doping concentration to cover the fins, thereby improving electrical control and reducing resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional fabrication methods are used for scaling down semiconductor devices, then manufacturing simplicity is maintained, but electrical control over the channel and resistance reduction are insufficient

Engineering Contradiction:
Improveelectrical controlVSAvoidfabrication process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by forming a strained material layer selectively over the semiconductor fin structure, creating localized strain in specific regions to enhance carrier mobility and electrical control without requiring complex global process changes

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses composite materials by combining the semiconductor fin material with a strained material layer having different crystal structure and doping characteristics, creating a composite structure that provides both mechanical strain and electrical doping benefits for improved device performance

Inventive Principle:
Principle #40Composite materials

2Productivity

If the semiconductor device is scaled down in size, then device density is improved, but electrical control and resistance management become more difficult

Engineering Contradiction:
Improvedevice densityVSAvoidelectrical control
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from planar 2D channel control to 3D vertical fin structure with wrap-around gate, adding a vertical dimension for carrier transport while the strained material layer provides an additional degree of freedom for electrical control through strain engineering in the scaled-down device

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If planar CMOS structure is used, then fabrication is simple, but electrical control over the channel is inadequate

Engineering Contradiction:
Improveelectrical controlVSAvoidfabrication simplicity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the channel into vertical fin structures separated by isolation regions, allowing independent control and strain engineering of each fin while maintaining overall process simplicity through standardized repetitive fabrication steps

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements nesting by forming the gate structure that wraps around the vertical fin channel, with the strained material layer nested within this gate structure, creating a multi-layer nested configuration that enhances control without proportionally increasing fabrication complexity

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the electrical control over the channel and reduces the total resistance of the FinFET by approximately 20%, improving device performance by about 10% compared to conventional methods.

Implementation Method 1

a strained material doped with a conductive dopant is formed to cover the semiconductor fin revealed by the gate stack, and the strained material is formed by selectively growing a bulk layer with a gradient doping concentration

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

the strained material is formed by selectively growing a bulk layer with a gradient doping concentration

Methodology Applied
Scientific EffectDoping: Dopants

Data Source

PatentUS9553191B1Fin field effect transistor and method for fabricating the same
Publication Date: 2017.01.24 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9553191B1 patent drawing
  • US9553191B1 patent drawing
  • US9553191B1 patent drawing

AI summary

A method of fabricating a FinFET includes at last the following steps. A semiconductor substrate is patterned to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin between the trenches. Insulators are formed in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. A strained material doped with a conductive dopant is formed over portions of the semiconductor fin revealed by the gate stack, and the strained material is formed by selectively growing a bulk layer with a gradient doping concentration.