FinFET Strained Material Volume Management via Cap Layer Segmentation
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Solution Overview
Problem
In the semiconductor industry, particularly for FinFETs, achieving a strained structure in recessed source/drain portions to enhance carrier mobility is challenging due to limitations in fin critical dimension, fin profile, and fin pitch, which affects device performance and yield, especially in memory regions where increased strained material volume can lead to unwanted connections.
Innovation Solution
A method is developed to fabricate semiconductor devices with increased strained material volume in device regions for improved performance while suppressing strained material volume in memory regions to prevent unwanted connections, using a gate-last process and selectively grown silicon germanium (SiGe) to enhance carrier mobility, with cap layers formed to connect strained materials in device regions but remain spaced in memory regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If strained material volume is increased to enhance carrier mobility and device performance, then charge mobility and drive strength are improved, but unwanted connections may occur in memory regions leading to reduced product yield
Solution Approach 1:
The patent applies local quality by forming different structures in different regions: in device regions, cap layers are formed to connect strained materials for enhanced carrier mobility, while in memory regions, the cap layers are spaced apart to prevent unwanted connections. This regional differentiation allows simultaneous optimization of device performance and prevention of yield-reducing defects.
Solution Approach 2:
The substrate is segmented into device regions and memory regions with different structural configurations. Device regions receive connected cap layers for performance enhancement, while memory regions receive spaced cap layers for yield protection. This segmentation strategy allows the system to achieve conflicting goals in different spatial locations.
2Productivity
If fin critical dimension and fin pitch are reduced to increase device density, then higher device density is achieved, but strained material volume is limited reducing carrier mobility enhancement
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change allows the channel to be controlled from both sides by the gate, effectively increasing the active channel volume and carrier mobility enhancement without increasing the footprint area, thereby maintaining high device density while improving strained material effectiveness.
Solution Approach 2:
The patent employs composite material structures including silicon germanium (SiGe) strained materials combined with silicon nitride cap layers. The SiGe layer provides strain-induced carrier mobility enhancement, while the silicon nitride cap layers provide structural support and enable the connection strategy. This composite approach allows simultaneous achievement of high device density and sufficient strained material volume.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves charge mobility and device performance by increasing strained material volume in device regions while maintaining product yield by avoiding unwanted connections in memory regions, achieving better drive strength and yield simultaneously.
Implementation Method 1
strained materials in recessed source/drain (S/D) portions of the FinFET utilizing selectively grown silicon germanium (SiGe) may enhance carrier mobility. The stress effects improve charge mobility through the channel
Implementation Method 2
Epitaxy semiconductor layers are thus formed on the fins to increase their volumes using epitaxy processes
Data Source
AI summary
An embodiment is a semiconductor device, comprising: a substrate; a plurality of fin structures disposed on the substrate; a plurality of first strained materials disposed on each of the plurality of the fin structures; a plurality of cap layers individually formed on each of the plurality of first strained materials, wherein at least two cap layers are connected to each other; a second strained material disposed on the at least two cap layers which are connected to each other.


