FinFET Strained Source/Drain Structure for Defect Reduction
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Solution Overview
Problem
The challenge in fabricating FinFETs is the presence of strain-induced crystal defects due to lattice mismatch, which can lead to device instability and failure as the gate length and spacing decrease.
Innovation Solution
A method is developed to fabricate a reduced-defect strained structure by forming a recess cavity in the substrate, followed by epi-growing a first strained layer adjacent to a dielectric film and then a second strained layer, trapping defects in the source and drain regions to enhance carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a strained structure is formed in FinFET source and drain regions to enhance carrier mobility, then device performance is improved, but strain-induced crystal defects increase due to lattice mismatch
Solution Approach 1:
A buffer layer is introduced as an intermediary between the substrate and the strained semiconductor layer. This buffer layer has a composition gradient that transitions from matching the substrate lattice to matching the strained layer lattice, thereby mediating the lattice mismatch and reducing strain-induced crystal defects while preserving the beneficial strain effects for carrier mobility enhancement
2Productivity
If gate length and spacing are decreased to increase device density, then productivity is improved, but strain-induced crystal defects increase leading to device instability
Solution Approach 1:
The composition parameters of the buffer layer are optimized with a graded structure where the semiconductor material composition gradually changes from substrate-matching to strained-layer-matching. This parameter gradient allows smaller gate lengths and spacing to be implemented while maintaining device stability by reducing crystal defects that would otherwise cause instability in high-density configurations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces crystal defects, enhancing carrier mobility and improving device performance by forming a strained structure with minimized defects.
Implementation Method 1
epi-growing a first strained layer in the lower portion of the recess cavity and then epi-growing a second strained layer in the upper portion of the recess cavity
Data Source
AI summary
A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.