FinFET Strained S/D Structure With Defect-Trapping Relaxation Layer
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating FinFETs due to strain-induced crystal defects in the lattice mismatch between the fin and strained portions, leading to device instability and potential failure, especially as gate length and spacing decrease.
Innovation Solution
A method is developed to fabricate a reduced-defect strained structure by forming a recess cavity in the substrate, growing a first strained layer as a relaxation layer to trap defects, and then growing a second strained layer in the upper portion of the cavity, using epitaxial processes like LPCVD for SiGe or SiC to enhance carrier mobility and reduce defect paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a strained structure is formed in the FinFET to enhance carrier mobility, then device performance is improved, but strain-induced crystal defects are generated due to lattice mismatch between the fin and strained portions
Solution Approach 1:
A relaxed strained layer is introduced as an intermediary between the substrate and the strained structure. This intermediate layer acts as a buffer that absorbs the lattice mismatch stress, preventing strain-induced crystal defects from forming in the strained structure while still allowing the desired strain effect to be maintained for enhanced carrier mobility.
Solution Approach 2:
The relaxed strained layer is formed preliminarily before forming the strained structure. By preparing this defect-absorbing layer in advance, the patent prevents the generation of crystal defects before they can compromise device reliability, thereby enabling safe implementation of strain engineering.
2Productivity
If gate length and spacing are decreased to increase device density, then productivity is improved, but strain-induced crystal defects increase leading to device instability
Solution Approach 1:
The relaxed strained layer serves as a protective intermediary that becomes increasingly important as device dimensions are scaled down. By absorbing lattice mismatch stresses, this intermediate layer prevents the amplification of strain-induced defects that would otherwise occur more frequently in smaller, denser devices, thereby maintaining device stability despite increased productivity.
3Reliability
If a relaxation layer is formed to trap defects, then device stability is improved, but additional fabrication steps are required increasing process complexity
Solution Approach 1:
The formation of the relaxed strained layer is merged with the existing strained structure fabrication process. By combining these two functions into a single integrated process flow, the patent achieves defect trapping and device stabilization without proportionally increasing process complexity, making the solution practical for manufacturing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces crystal defects in the strained structure, enhancing carrier mobility and improving device performance by eliminating defect pathways, thereby stabilizing the FinFET operation.
Implementation Method 1
growing a first strained layer as a relaxation layer to trap defects, and then growing a second strained layer in the upper portion of the cavity, using epitaxial processes like LPCVD for SiGe or SiC
Data Source
AI summary
A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.