FinFET Strained Silicon Integration for Mobility and Leakage Control
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Solution Overview
Problem
Conventional MOSFETs face challenges in scaling due to short channel effects, mobility degradation, and process issues as gate lengths are reduced below 100 nm, necessitating new device structures for improved performance and further device scaling.
Innovation Solution
The integration of finFET transistor devices is achieved by forming compressive strained silicon germanium (SiGe) and tensile strained silicon layers through a process involving epitaxial growth, implantation, and annealing to create fin structures, enabling enhanced channel mobility for both n-type and p-type transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar MOSFETs are scaled to reduce gate length below 100 nm, then device density and integration capacity are improved, but short channel effects cause excessive leakage and mobility degradation worsen
Solution Approach 1:
The patent transitions from planar 2D channel structure to 3D vertical finFET structure. The channel is formed as a vertical fin extending from the substrate surface, allowing the gate to control the channel from three sides (top and two lateral sides). This dimensional change provides better electrostatic control over the channel, suppressing short channel effects while maintaining scaled dimensions.
Solution Approach 2:
The patent employs composite material structures including strained silicon layers combined with silicon germanium (SiGe) sacrificial layers. The strained silicon provides enhanced carrier mobility in the channel, while the SiGe layers serve as sacrificial structures during fabrication that are later removed to form the fin structure. This composite approach simultaneously improves device performance and enables the finFET geometry.
2Productivity
If gate length is reduced to increase device density, then more devices can be integrated, but mobility degradation increases making it difficult to maintain device performance
Solution Approach 1:
The patent changes the physical state and mechanical properties of the silicon channel by introducing strain through dislocationless transformation from SiGe. This strain modification alters the band structure of silicon, enhancing carrier mobility without requiring changes to the fundamental silicon material properties. The strain is maintained through the finFET geometry and selective removal of SiGe layers.
Solution Approach 2:
The vertical fin structure creates a three-dimensional channel where carriers move primarily in the horizontal direction while the gate provides control from multiple directions. This geometric configuration reduces the impact of scattering mechanisms that limit mobility in planar devices, allowing better mobility retention at scaled dimensions.
3Length of moving object
If finFET structures are formed using conventional processes, then device scaling is achieved, but process complexity increases and manufacturing challenges arise
Solution Approach 1:
The patent performs preliminary actions by forming the strained silicon and SiGe layers through epitaxial growth before the fin patterning step. The SiGe layers are deposited with specific thicknesses and compositions that pre-determine the final fin geometry. This preliminary structuring simplifies subsequent processing by eliminating the need for complex sacrificial layer deposition and removal steps that would be required if fins were formed directly.
Solution Approach 2:
The SiGe layers serve multiple functions: they act as sacrificial structures defining the fin geometry, provide strain to the silicon channel for mobility enhancement, and serve as etch stop layers during processing. This multi-functionality reduces the number of separate process steps needed, simplifying the overall fabrication sequence despite the advanced device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electron and hole mobility, improving device performance and allowing for further scaling of ultra-large scale integrated circuit devices by reducing short channel effects and mobility degradation.
Implementation Method 1
subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer
Implementation Method 2
performing an annealing process so as to recrystallize the rSiGe layer
Implementation Method 3
epitaxially growing a tensile strained silicon layer on the rSiGe layer
Data Source
AI summary
A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.