FinFET Strained Spacer Structure for Higher NFET Channel Mobility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional gate spacers in FinFETs are not entirely satisfactory in providing adequate stress to enhance electron mobility and switching speed in N-type channel regions, limiting the performance of semiconductor devices.
Innovation Solution
A strained spacer is formed over N-type gate structures in FinFETs through a process involving the deposition, recessing, and annealing of specific spacers to exert tensile stress on the N-type channel region, improving electron mobility and drain current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional unstrained spacers are used, then the device structure is simple and manufacturing is easier, but electron mobility and drain current are insufficient
Solution Approach 1:
The patent applies parameter changes by transitioning the spacer material from an unstrained state to a strained state through controlled annealing processes. This changes the physical properties of the spacer material, inducing tensile stress that directly improves electron mobility in the channel region without fundamentally altering the device architecture
Solution Approach 2:
The patent utilizes phase transitions during the annealing process, where the spacer material undergoes structural changes at specific temperature ranges. This phase transition induces the desired tensile stress in the channel while maintaining the overall spacer structure integrity
2Productivity
If strained spacers are implemented, then electron mobility and drain current are enhanced, but the manufacturing process becomes more complex
Solution Approach 1:
The patent implements preliminary action by forming the spacer structure with appropriate material composition and geometry before the annealing process. This preliminary preparation ensures that when annealing occurs, the desired tensile stress is automatically induced without requiring additional complex processing steps
Solution Approach 2:
The patent controls the annealing parameters (temperature, time, atmosphere) to achieve the desired strain state. By optimizing these parameters, the process induces sufficient tensile stress for improved drain current while keeping the manufacturing process within practical limits
3Speed
If strained spacers are used, then switching speed increases, but the processing complexity increases
Solution Approach 1:
The patent merges the spacer formation process with the existing fabrication sequence, integrating the strain induction step into the standard manufacturing flow. This combination approach achieves improved switching speed while minimizing the addition of separate processing steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The strained spacer increases electron mobility and switching speed in N-type channel regions, leading to enhanced performance of semiconductor devices without degrading P-type device performance.
Implementation Method 1
The strained spacer can cause a tensile stress exerted on the N-type channel region
Implementation Method 2
Replacing unstrained spacers with strained spacers through annealing
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.