FinFET Strained Spacer Layout for Faster N-Type Switching
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Solution Overview
Problem
Conventional gate spacers in FinFETs are not entirely satisfactory in providing adequate stress to enhance electron mobility and switching speed in N-type channel regions, limiting the performance of semiconductor devices.
Innovation Solution
A strained spacer is formed over N-type gate structures in FinFETs through a process involving the deposition, recessing, and annealing of specific spacers to exert tensile stress on the N-type channel region, improving electron mobility and drain current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional gate spacers are used in FinFETs, then the gate structures are isolated and protected during fabrication, but the electron mobility and switching speed in N-type channel regions are not sufficiently enhanced
Solution Approach 1:
The patent applies different stress conditions to different device regions by forming a strained spacer selectively over the N-type gate structure while leaving the P-type gate structure with a conventional unstrained spacer. This local differentiation enables enhanced electron mobility in N-type channels through tensile stress without affecting P-type device performance
Solution Approach 2:
The patent changes the physical state and mechanical properties of the spacer material by subjecting it to annealing processes that induce tensile stress. The spacer material parameters are modified to create a strained state that exerts mechanical stress on the underlying N-type channel region, thereby enhancing carrier mobility and switching speed
2Speed
If a strained spacer is formed to enhance electron mobility in N-type channels, then switching speed improves, but the device fabrication process becomes more complex
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming a first spacer over both gate structures, selectively removing the first spacer over the N-type gate structure, and forming a second strained spacer only over the N-type gate structure. This segmentation allows the strained spacer to be integrated into the existing fabrication flow without requiring complete process redesign
Solution Approach 2:
The first unstrained spacer is formed as a preliminary structure that serves as a template and protective layer during subsequent processing. This preliminary spacer enables selective spacer formation and protects the gate structures during the strained spacer formation process, simplifying the overall fabrication sequence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The strained spacer increases electron mobility and switching speed in N-type channel regions, leading to enhanced performance by applying tensile stress, while maintaining performance in P-type regions.
Implementation Method 1
The strained spacer can be annealed and strained to become compressively strained, and the compressively strained spacer can exert a tensile stress on the N-type channel region
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. A semiconductor device according to an embodiment includes a P-type field effect transistor (PFET) and an N-type field effect transistor (NFET). The PFET includes a first gate structure formed over a substrate, a first spacer disposed on a sidewall of the first gate structure, and an unstrained spacer disposed on a sidewall of the first spacer. The NET includes a second gate structure formed over the substrate, the first spacer disposed on a sidewall of the second gate structure, and a strained spacer disposed on a sidewall of the first spacer.