FinFET Strained Well Regions for Mobility Enhancement

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Solution Overview

Problem

Current FinFET technologies face limitations in enhancing drive currents due to low electron and hole mobility in channel regions, particularly in NMOS and PMOS transistors, which restricts the performance of metal-oxide-semiconductor transistors.

Innovation Solution

The formation of strained well regions in FinFETs is achieved by growing semiconductor regions with varying germanium content through epitaxy, introducing tensile strain and conduction band differences to create a conduction band well, which increases electron mobility and forms high-density Two-Dimensional Electron Gas channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If conventional FinFET channel regions are used, then the device structure is simple, but electron and hole mobility are low, limiting drive current

Engineering Contradiction:
Improveelectron and hole mobilityVSAvoidchannel region structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent introduces strained well regions specifically in the channel area of the FinFET, creating localized strain in the semiconductor lattice. This local modification of the channel region structure enhances carrier mobility without requiring strain throughout the entire device, thus improving electron and hole mobility while maintaining reasonable device complexity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs composite semiconductor structures including silicon-germanium (SiGe) layers combined with silicon layers to form the strained well regions. This composite material approach enables the channel to exhibit enhanced mobility properties through the strained SiGe regions while maintaining compatibility with standard silicon processing, resolving the contradiction between improved mobility and device complexity

Inventive Principle:
Principle #40Composite materials

2Speed

If germanium content is increased to enhance mobility, then electron and hole mobility improve, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecarrier mobilityVSAvoidgermanium content control
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent systematically varies the germanium content parameter across different layers of the strained well structure. By controlling the germanium concentration gradient and using multiple layers with different germanium percentages, the patent optimizes mobility enhancement while managing the complexity of germanium content control through a structured parameter variation approach

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent divides the channel region into multiple discrete layers with varying germanium content rather than using a single uniform composition. This segmentation allows independent optimization of each layer's germanium content to achieve desired mobility characteristics while simplifying the overall manufacturing control through modular layer-by-layer fabrication

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly enhances the saturation current of FinFETs by creating a conduction band well with tensile strain, allowing electrons to move freely and increasing drive currents, thereby improving transistor performance.

Implementation Method 1

growing semiconductor regions with varying germanium content through epitaxy

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Implementation Method 2

introducing tensile strain and conduction band differences to create a conduction band well, which increases electron mobility

Methodology Applied
Scientific EffectStrain effect: Deformation

Data Source

PatentUS10158015B2FinFETs with strained well regions
Publication Date: 2018.12.18 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10158015B2 patent drawing
  • US10158015B2 patent drawing
  • US10158015B2 patent drawing

AI summary

A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.