FinFET Stress Layers Enhance Carrier Mobility
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Solution Overview
Problem
Existing semiconductor technologies face challenges in enhancing carrier mobility in FinFETs due to material changes, growth defects, and compatibility issues with CMOS devices, particularly in sub-20 nm technology nodes where three-dimensional multi-gate devices require increased stress for improved performance.
Innovation Solution
A semiconductor device and manufacturing method involving fins with stress layers of different materials, where the stress layers have connected parts that enclose channel regions, enhancing all-round stress and carrier mobility, using materials like Si, SiGe, SiSn, and Si:C, and forming metal silicide in source and drain regions to increase device drive capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If global strained fins or high mobility substrate materials are used to enhance carrier mobility, then carrier mobility in the channel region is improved, but technical difficulties arise including change of energy level, change of density of states, change of carrier concentration, growth defects, and compatibility issues with CMOS devices
Solution Approach 1:
The device is divided into distinct regions: channel regions made of first material (e.g., Si) and source/drain regions made of second material (e.g., SiGe or Si:C). This segmentation allows each region to be optimized independently - the channel maintains compatibility with CMOS technology while the source/drain regions provide the necessary stress to enhance carrier mobility without introducing the problematic effects of global strain or high mobility substrate materials throughout the entire device
Solution Approach 2:
Different materials are used in different locations within the device. The channel regions use first material suitable for CMOS compatibility, while the source/drain regions use second material with different properties (higher stress, different band structure) to locally enhance carrier mobility. This local quality approach allows stress enhancement without the global effects that cause technical difficulties
2Reliability
If embedded SiGe source/drain or tensile stress contact etch stop layer is used to provide compressive stress in PMOS device, then carrier mobility is enhanced, but process complexity increases with multiple generations of source/drain stress memorization techniques
Solution Approach 1:
The invention segments the device into channel and source/drain regions with different materials. By forming source/drain regions of second material (e.g., SiGe, Si:C) directly in the trenches adjacent to the channel regions, the stress memorization function is achieved through a single material selection rather than multiple generations of complex CESL and e-SiGe combinations, thereby reducing process complexity while maintaining carrier mobility enhancement
Solution Approach 2:
The device uses composite material structure with first material (e.g., Si) for channels and second material (e.g., SiGe, Si:C) for source/drain regions. This composite approach provides the necessary stress for carrier mobility enhancement in a more straightforward manner compared to the multi-generation stress memorization techniques, reducing process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances carrier mobility and drive capability by forming annular stereo strain channel regions with high-stress silicide alloy, increasing stress in channel regions and improving device performance.
Implementation Method 1
the stress layers have connected parts in the fins and the channel regions enclose the connected parts
Implementation Method 2
selectively epitaxially growing stress fins comprised of above mentioned high mobility materials or strained materials
Data Source
AI summary
The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts.