FinFET Stress Material Layout for Capacitance Reduction
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Solution Overview
Problem
FinFET devices face challenges with high Ceff and ineffectiveness of conventional stress elements, such as eSiGe or stress liners, which hinder performance due to increased gate-to-EPI capacitance and external resistance in non-fin areas.
Innovation Solution
Incorporating an insulator stress material with a lattice constant different from the gate material between and around finFET structures, which reduces Ceff and imparts stress to the channel, eliminating gate-to-EPI capacitance and enhancing device performance by using stress materials that are insulators, like nitride, and depositing conductive layers for improved conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If conventional stress elements (eSiGe or stress liner) are used in finFET devices, then stress is provided to the channel, but Ceff increases due to gate-to-EPI capacitance in non-fin areas
Solution Approach 1:
The patent extracts the conductive stress element from the non-fin areas, removing the source of gate-to-EPI capacitance. The stress function is retained only in the fin regions where it is needed, while the non-fin areas use insulator material that does not create harmful capacitance.
Solution Approach 2:
The patent applies different material properties to different spatial locations: conductive stress material (eSiGe) is applied only to the fin regions where stress is needed, while insulator material is used in the non-fin areas where capacitance would be harmful. This local differentiation resolves the contradiction between providing stress and avoiding capacitance.
2Reliability
If finFET or trigate devices merge in the source drain area to reduce external resistance, then conductivity is improved, but Ceff increases due to finite gate-to-EPI capacitance
Solution Approach 1:
The patent removes the conductive material from the non-fin source drain areas, eliminating the gate-to-EPI capacitance source. The conductive merge is maintained only in the fin regions where it provides useful low resistance, while insulator material is used in the non-fin regions.
Solution Approach 2:
The patent creates local differentiation in the source drain structure: conductive material is present only where it serves the dual purpose of providing low resistance and necessary stress, while insulator material is used where only capacitance would result.
3Object-generated harmful factors
If insulator stress material is used between adjacent finFET structures, then Ceff is reduced by eliminating gate-to-EPI capacitance, but stress application may be reduced
Solution Approach 1:
The patent applies insulator stress material specifically in the non-fin areas between adjacent finFET structures, where it eliminates capacitance without interfering with stress application in the fin regions. The fin regions retain their conductive stress material, while the intervening non-fin areas use insulator material for capacitance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively lowers Ceff and enhances stress in finFET devices, improving switching speed and current density while eliminating gate-to-EPI capacitance, leading to better control over the channel and reduced external resistance.
Implementation Method 1
The insulator stress material has a lattice constant different than that of the gate material used for the plurality of finFET gate structures
Data Source
AI summary
A finFET structure and method of manufacture such structure is provided with lowered Ceff and enhanced stress. The finFET structure includes a plurality of finFET structures and a stress material forming part of a gate stack and in a space between adjacent ones of the plurality of finFET structures.