FinFET Stress Memorization for Uniform Dislocation Strain
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Solution Overview
Problem
Existing strain engineering methods for transistor devices are not entirely satisfactory in achieving uniform stress distribution and carrier mobility enhancement across all crystal planes, leading to non-uniform dislocations and suboptimal device performance.
Innovation Solution
The method involves forming amorphized regions in the source and drain areas of FinFET devices, followed by the deposition of a stressor layer using an ALD-based process to smooth the amorphous-crystalline interface, and subsequent annealing to recrystallize these regions, resulting in uniformly distributed dislocations that exert tensile stress and enhance carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing strain engineering methods are applied to transistor devices, then carrier mobility enhancement is achieved, but uniform stress distribution across crystal planes is not achieved
Solution Approach 1:
The patent changes the crystallographic orientation parameter of the semiconductor fin from conventional <100> to <110>, which fundamentally alters how stress propagates through the crystal lattice. This parameter change enables uniform stress distribution across all crystal planes, resolving the non-uniform stress problem while maintaining carrier mobility enhancement
Solution Approach 2:
The patent employs a composite structure combining silicon substrate with epitaxially grown silicon layers having different crystallographic orientations. This composite approach allows precise control over dislocation formation and stress distribution, achieving uniform stress across crystal planes while enhancing device performance
2Reliability
If existing strain engineering methods are applied, then some carrier mobility improvement is achieved, but non-uniform dislocations are formed
Solution Approach 1:
By changing the fin crystallographic orientation to <110> and controlling epitaxial growth parameters, the patent achieves uniform dislocation formation. The specific crystallographic parameter change ensures that dislocations form symmetrically and uniformly, eliminating the non-uniform dislocation problem while maintaining high carrier mobility
Solution Approach 2:
The patent applies different crystallographic orientations to different regions of the semiconductor structure. The <110> oriented fins provide uniform dislocation characteristics, while the epitaxial layers provide the necessary stress. This local quality differentiation achieves both uniform dislocations and high carrier mobility
3Ease of manufacture
If conventional fin structures are used, then manufacturing is simpler, but stress uniformity across crystal planes is insufficient
Solution Approach 1:
The patent modifies the crystallographic orientation parameter of the fin from <100> to <110>, which maintains compatibility with conventional CMOS manufacturing processes while achieving the critical improvement of uniform stress distribution across all crystal planes. This parameter change enables stress uniformity without significantly complicating fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform channel stress and improved carrier mobility in transistor devices by forming symmetric dislocations during recrystallization, thereby enhancing device performance.
Implementation Method 1
the deposition of a stressor layer using an ALD-based process to smooth the amorphous-crystalline interface
Implementation Method 2
subsequent annealing to recrystallize these regions, resulting in uniformly distributed dislocations
Implementation Method 3
using ion species to damage exposed surface of the semiconductor fin not covered by the sacrificial gate structure
Implementation Method 4
forming a stressor layer with tensile stress over the exposed surface of the semiconductor fin, subjecting the exposed surface of the semiconductor fin to an annealing process to impart stress from the stressor layer
Data Source
AI summary
A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a method for forming a semiconductor device structure is provided. The method includes forming a sacrificial gate structure over a portion of a semiconductor fin, using ion species to damage exposed surface of the semiconductor fin not covered by the sacrificial gate structure, forming a stressor layer with tensile stress over the exposed surface of the semiconductor fin, subjecting the exposed surface of the semiconductor fin to an annealing process to impart stress from the stressor layer to the semiconductor fin, removing the stressor layer, forming a recess in the semiconductor fin not covered by the sacrificial gate structure, and forming a source/drain region in the recess.