FinFET Stressor Uniformity via Local Material Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing methods for applying stress to channel regions of FET devices are affected by pattern-loading effects, which occur due to differences in pattern densities during the etching of semiconductor substrates, leading to inconsistent stressor profiles and reduced performance.
Innovation Solution
The method involves forming fins with different semiconductor materials in different regions, allowing for simultaneous etching that offsets pattern-loading effects by varying the etch rates, resulting in distinct recess profiles and epitaxial source/drain regions with specific thicknesses and proximity distances, thereby improving stress application uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stressors are grown in source and drain regions using conventional methods, then carrier mobility is improved through stress application, but pattern-loading effects cause inconsistent stressor profiles across different device regions
Solution Approach 1:
The patent applies different semiconductor materials (e.g., SiGe, SiC) to different fin regions based on their specific stress requirements. Core logic region fins receive materials optimized for high-performance transistors, while I/O region fins receive materials optimized for high-voltage devices. This local differentiation eliminates pattern-loading effects by ensuring each region receives the appropriate stress characteristics without being influenced by neighboring patterns.
Solution Approach 2:
The substrate is divided into distinct regions (core logic region and I/O region) with different fin structures and stressor materials. By segmenting the device into region-specific units with tailored stress characteristics, the patent prevents cross-contamination of stress patterns and ensures consistent stress application within each functional block.
2Productivity
If simultaneous etching is performed on regions with different pattern densities, then manufacturing efficiency is maintained, but pattern-loading effects cause varying etch rates and inconsistent trench profiles
Solution Approach 1:
Different semiconductor materials are deposited in different regions to compensate for pattern-loading effects during simultaneous etching. Regions with higher pattern density receive materials etched at rates that match their local pattern characteristics, while lower density regions receive materials optimized for their spacing. This ensures uniform trench profiles across the entire wafer despite varying pattern densities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of integrated circuits by achieving more consistent stress distribution across different device regions, improving performance and reliability, particularly in core logic and I/O regions.
Implementation Method 1
simultaneous etching that offsets pattern-loading effects by varying the etch rates
Implementation Method 2
epitaxially growing stressors in the recesses
Data Source
AI summary
In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region.