FinFET Stressor Reflow for Void-Free Channel Mobility
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Solution Overview
Problem
In advanced semiconductor manufacturing, the narrow window between fin extensions in FinFETs due to epitaxial SiGe formation leads to bridging and voids in the inter metal dielectric layer, and the selective epitaxy growth on ultra-narrow fin widths is inefficient, complicating the integration of stressor techniques for enhanced mobility.
Innovation Solution
The process involves forming SiGe fin extensions on FinFETs with a reduced STI dielectric height, followed by depositing a conformal stressor dielectric material that is reflowed to fill the space between fins, applying stress to the channel while forming sidewall spacers, without requiring additional masks or photo steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial SiGe formation is performed on ultra-narrow fin widths, then fin extensions are formed to enhance device performance, but the window between fin extensions becomes too narrow causing bridging and voids in the inter metal dielectric layer
Solution Approach 1:
The patent segments the fin structure by forming discrete fin extensions on top of each fin rather than continuous extensions, which maintains the window spacing between fins. This segmentation approach allows SiGe formation without causing bridging between adjacent fins, resolving the contradiction between enhancing device performance and maintaining manufacturing precision.
Solution Approach 2:
The patent applies SiGe material locally only to the top surfaces of individual fins where fin extensions are formed, rather than attempting continuous coverage. This local quality approach ensures that each fin receives the mobility-enhancing SiGe stressor while preventing material bridging between fins, thus maintaining both device performance and window spacing.
2Reliability
If selective epitaxy growth is used on ultra-narrow fin widths, then fin extensions can be formed, but the process becomes inefficient and complex
Solution Approach 1:
The patent performs preliminary actions by first forming a sacrificial mandrel layer and defining fin patterns before performing the epitaxial SiGe growth. This preliminary structuring creates well-defined growth templates that simplify the subsequent epitaxy process, improving efficiency by preventing unwanted growth and reducing the need for complex selective growth conditions.
Solution Approach 2:
The patent introduces a mandrel layer as an intermediary structure that facilitates the epitaxial growth process. This intermediary layer serves as a template and protective barrier during SiGe formation, enabling efficient and controlled growth on ultra-narrow fins without direct complex selective epitaxy, thus improving productivity.
3Reliability
If complex stressors such as selective SiGe source/drain structures are used, then hole mobility in PMOS devices is enhanced, but additional processing operations and costs increase
Solution Approach 1:
The patent merges the fin extension formation and stressor application into a single epitaxial SiGe growth step. By combining these functions into one process, the patent eliminates the need for separate complex stressor formation steps while still achieving the desired hole mobility enhancement, thus reducing device complexity and processing operations.
Solution Approach 2:
The epitaxial SiGe layer serves multiple functions simultaneously: it forms the fin extension structure, provides the stressor for mobility enhancement, and defines the lateral boundaries of the active region. This multi-functionality eliminates the need for separate selective SiGe source/drain structures and their associated complex processing, reducing both device complexity and processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method increases channel stress without voids in the inter metal dielectric layer, facilitates die singulation, and enhances mobility by maintaining a sufficient window between fin extensions, improving device performance and efficiency.
Implementation Method 1
The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET
Implementation Method 2
An epitaxial process is performed on the fins 106, forming a SiGe layer 106e over the fin 106 of the finFET
Data Source
AI summary
A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.