FinFET Semiconductor Strip Structural Stability

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Solution Overview

Problem

The scaling down of Integrated Circuit (IC) technology leads to increased complexity in processing and manufacturing, particularly in the formation of Fin Field-Effect Transistors (FinFETs), where high-aspect ratio semiconductor strips are prone to bending or peeling, resulting in yield loss and performance degradation.

Innovation Solution

A method involving the formation of semiconductor strip bases with reduced aspect ratios is achieved by etching trenches in a semiconductor substrate, using hard masks to control the etching process, and forming isolation regions to create semiconductor fins with a gate stack, thereby reducing the likelihood of strip bending and peeling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If high-aspect ratio semiconductor strips are used to maintain strip height during scaling, then the FinFET performance is improved, but the strips become prone to bending and peeling during processing

Engineering Contradiction:
Improvesemiconductor strip heightVSAvoidstrip structural stability
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The semiconductor strip is segmented into multiple sections along its length, with each section having a separate support structure (isolation region) beneath it. This segmentation allows each section to be independently supported, preventing bending and peeling while maintaining the overall strip height needed for FinFET performance.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Isolation regions are formed beneath the semiconductor strip before the strip is fully processed. This preliminary action provides structural support to the strip in advance, preventing bending and peeling issues that would occur during subsequent processing steps and device operation.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If semiconductor strip height is increased to improve FinFET performance, then device performance is enhanced, but manufacturing complexity increases

Engineering Contradiction:
ImproveFinFET performanceVSAvoidprocessing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The isolation regions are merged with the substrate formation process, combining multiple functions (substrate preparation, structural support, and device isolation) into a single integrated structure. This merging reduces manufacturing complexity while enabling the use of high-aspect ratio strips for improved FinFET performance.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If aspect ratio of semiconductor strips is reduced to prevent bending, then manufacturing yield is improved, but strip height must be compromised

Engineering Contradiction:
Improvemanufacturing yieldVSAvoidsemiconductor strip height
Core Design Contradiction:
ProductivityVSLength of moving object

Solution Approach 1:

Instead of changing the aspect ratio by reducing strip height in the vertical dimension, the solution introduces a new dimensional approach by placing support structures (isolation regions) in the horizontal plane beneath the strip. This allows the strip to maintain its full height while preventing bending through lateral support.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10727314B2FinFET with a semiconductor strip as a base
Publication Date: 2020.07.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10727314B2 patent drawing
  • US10727314B2 patent drawing
  • US10727314B2 patent drawing

AI summary

A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip located between two neighboring ones of the recesses, forming a second hard mask on sidewalls of the semiconductor strip, performing a first anisotropic etch on the second hard mask to remove horizontal portions of the second hard mask, and performing a second anisotropic etch on the semiconductor substrate using the first hard mask and vertical portions of the second hard mask as an etching mask to extend the recesses down. The method further includes removing the vertical portions of the second hard mask, and forming isolation regions in the recesses. The isolation regions are recessed, and a portion of the semiconductor strip between the isolation regions protrudes higher than the isolation regions to form a semiconductor fin.