FinFET Parasitic Capacitance Reduction via Substrate Depletion
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Solution Overview
Problem
Semiconductor devices like FinFETs suffer from parasitic capacitance, which degrades high-frequency performance due to close proximity between device components and the substrate, limiting maximum operation speed.
Innovation Solution
A substrate depletion region is created by forming a deep N-well or P-well in the substrate and applying a bias voltage to increase the electrical distance between the FinFET device and the substrate, reducing parasitic capacitance through the formation of an insulating region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the FinFET device is formed close to the substrate to reduce device size, then device integration density is improved, but parasitic capacitance increases degrading high-frequency performance
Solution Approach 1:
A deep N-well structure is introduced as an intermediary between the FinFET device and the P-type substrate. This deep N-well acts as a mediator that electrically isolates the device from the substrate, reducing parasitic capacitance while allowing the device to maintain its compact footprint close to the substrate surface.
Solution Approach 2:
The solution moves from a two-dimensional planar isolation approach to a three-dimensional vertical isolation approach by forming a deep N-well extending significantly into the substrate. This vertical dimension provides electrical isolation without increasing the horizontal footprint of the device.
2Object-affected harmful factors
If a deep N-well is formed to reduce parasitic capacitance, then high-frequency performance is improved, but device complexity increases
Solution Approach 1:
The deep N-well structure serves multiple functions simultaneously: it reduces parasitic capacitance between the device and substrate, provides electrical isolation, and can serve as a substrate biasing structure. This multi-functionality reduces the need for additional separate structures, thereby limiting the increase in overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases the electrical distance by 10 times, resulting in a 10 times decrease in parasitic capacitance, thereby enhancing high-frequency performance and operation speed of FinFET devices.
Implementation Method 1
A substrate depletion region is created by forming a deep N-well or P-well in the substrate and applying a bias voltage to increase the electrical distance between the FinFET device and the substrate
Data Source
AI summary
A semiconductor device comprising a substrate and a transistor comprising a source, drain, and gate formed on the substrate. The semiconductor device further comprises a deep well formed in the substrate at a predetermined distance below the surface of the substrate and a contact configured to electrically couple the deep well to a voltage source such that a voltage can be applied to the deep well to create a substrate depletion region for reducing parasitic capacitance between the transistor and the substrate.