Air-Gap Isolation Layers in FinFETs for Substrate Stress Retention

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Solution Overview

Problem

Current semiconductor devices face challenges in applying sufficient stress to improve current driving capability due to compressive stress from oxide gap-filled isolation layers, which relieves stress in PMOS and NMOS devices, leading to mobility deterioration and performance issues.

Innovation Solution

The semiconductor device incorporates isolation layers with air gaps and a capping layer, where the isolation layers are narrower than the fin body, and the fin is formed separately to minimize stress relief, allowing for sufficient tensile or compressive stress application to both PMOS and NMOS devices, enhancing current driving capability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If isolation layers are made wider to improve isolation, then isolation effect is improved, but stress application to substrate is reduced

Engineering Contradiction:
Improveisolation effectVSAvoidstress application
Core Design Contradiction:
ReliabilityVSForce

Solution Approach 1:

The patent applies local quality by making the isolation layer narrower than the fin body width. This localized narrowing allows the isolation layer to provide sufficient electrical isolation while minimizing its mechanical footprint, thereby enabling effective stress application to the substrate in the active region without being diluted by excessive isolation layer width.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240072171A1Semiconductor device and method for fabricating the same
Publication Date: 2024.02.29 SK HYNIX INC
  • US20240072171A1 patent drawing
  • US20240072171A1 patent drawing
  • US20240072171A1 patent drawing

AI summary

Various embodiments of the present invention are to provide a semiconductor device and a method for fabricating the same and, more particularly, to a semiconductor device including isolation layers including an air gap, thereby minimizing stress to a substrate caused by oxide and improving performance of a device, and a method for fabricating the same. The semiconductor device according to the embodiment of the present invention comprises: a plurality of isolation layers each including a trench formed in a substrate and an air gap in a lower portion of the trench; an active region including a fin body disposed between the isolation layers, which are consecutively disposed, and a fin formed on the fin body, the fin having a narrower width than the fin body and extending in a first direction; a gate structure partially covering the active region and the isolation layers, and extending in a second direction; and a source/drain region covering the fin on both sides of the gate structure.