FinFET Source Drain Superlattice Reduces Contact Resistance
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Solution Overview
Problem
Current semiconductor devices face limitations in achieving enhanced performance due to high source and drain contact resistance, which affects mobility and efficiency.
Innovation Solution
The implementation of a dopant diffusion blocking superlattice in the source and drain regions of FINFETs, comprising stacked semiconductor and non-semiconductor monolayers, reduces Schottky barrier height and contact resistance by trapping dopants and immobilizing point defects, thereby improving charge carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional source and drain regions are used in FINFETs, then the device structure is simple and easy to manufacture, but the contact resistance is high which reduces charge carrier mobility and device performance
Solution Approach 1:
The source and drain regions are segmented into multiple sub-regions by inserting superlattice layers at specific depths. Each superlattice layer divides the doped region into upper and lower portions, creating a multi-layered structure that reduces contact resistance while maintaining manufacturability through controlled epitaxial growth and doping processes
Solution Approach 2:
Composite superlattice structures comprising alternating layers of semiconductor materials (e.g., Si/SiGe) are integrated into the source and drain regions. These composite materials provide both mechanical support and electrical functionality, reducing Schottky barrier height and contact resistance while maintaining structural integrity
2Reliability
If dopant concentration is increased to reduce contact resistance, then contact resistance decreases, but dopant diffusion into the channel region increases which degrades device performance
Solution Approach 1:
Superlattice layers are positioned as intermediary structures between the heavily doped source/drain regions and the channel. These intermediate layers act as diffusion barriers that prevent dopant atoms from migrating into the channel region while allowing electrical contact to be established, thus resolving the conflict between reducing contact resistance and preventing dopant diffusion
Solution Approach 2:
The superlattice layers are strategically positioned at specific depths within the source and drain regions, creating local variations in material properties. The layers have different compositions and structures tailored to provide dopant diffusion blocking at the channel interface while maintaining good electrical contact properties at the metal contact interface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces source and drain contact resistance, enhances charge carrier mobility, and provides a direct energy bandgap for improved opto-electronic device performance, while also acting as a barrier to dopant and material diffusion.
Implementation Method 1
dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region
Implementation Method 2
reduces Schottky barrier height and contact resistance by trapping dopants and immobilizing point defects
Implementation Method 3
Si—Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice
Implementation Method 4
the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer
Implementation Method 5
at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions
Data Source
AI summary
A FINFET may include a semiconductor fin, spaced apart source and drain regions in the semiconductor fin with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.