FinFET Surface Layer Selective Epitaxy for CMOS Compatibility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current methods for manufacturing FinFET structures face challenges in improving carrier mobility and compatibility with CMOS processes, particularly with the use of high mobility materials like Ge, GaAs, and InP, which result in devices with poor reliability and performance due to defects and incompatibility with standard CMOS processes.
Innovation Solution
A method involving the formation of a high mobility surface layer on the fins of FinFETs using selective epitaxial growth, comprising materials such as Ge, GaAs, InP, and their combinations, to enhance carrier mobility and device reliability, while maintaining compatibility with CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high mobility materials (Ge, GaAs, InP) are used to improve carrier mobility, then device driving capability increases significantly, but compatibility with CMOS processes deteriorates and device reliability decreases due to defects
Solution Approach 1:
The patent applies local quality by forming high mobility material layers selectively only in the channel region of the FinFET device, while other regions maintain standard CMOS materials. This allows the device to benefit from high carrier mobility in the channel without requiring complete process re-engineering, thus maintaining CMOS compatibility while improving performance.
Solution Approach 2:
The patent uses composite material structures by combining high mobility materials (Ge, GaAs, InP) with standard silicon-based CMOS materials in a multi-layer fin structure. This composite approach enables the device to leverage the advantages of both material systems - high mobility where needed and CMOS compatibility where standard processes are required.
2Reliability
If thick bulk layers of high mobility material are epitaxially formed on Si substrate, then carrier mobility improves, but manufacturing complexity increases and device reliability decreases due to defects
Solution Approach 1:
The patent segments the fin structure into multiple thin layers with different materials and orientations. Instead of using a single thick bulk layer of high mobility material, the fin is divided into alternating layers of high mobility material and silicon, with different crystal orientations. This segmentation reduces defect accumulation while maintaining high carrier mobility and simplifies the epitaxial growth process.
Solution Approach 2:
The patent applies partial action by incorporating high mobility material layers only in specific portions of the fin structure (the channel region) rather than throughout the entire device. This partial implementation achieves the desired mobility enhancement without requiring complete process re-engineering, thereby reducing manufacturing complexity while improving device reliability.
3Reliability
If high mobility material films are selectively epitaxially formed on Si substrate with isolation structure, then carrier mobility improves, but compatibility with gate-last process of HK gate dielectric/Metal Gate deteriorates
Solution Approach 1:
The patent applies preliminary action by forming the high mobility material layers in the fin structure before the gate stack is deposited. This timing allows the high mobility channels to be established early in the process, enabling subsequent gate-last processing steps (including HK dielectric and metal gate formation) to proceed using standard CMOS-compatible techniques without compromising the mobility-enhanced channel structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The selective epitaxial growth of high mobility materials on the fins effectively improves carrier mobility and device performance, enhancing reliability and compatibility with CMOS processes.
Implementation Method 1
forming a surface layer on the fin by selective epitaxial growth
Data Source
AI summary
A semiconductor device includes a fin extending on a substrate along a first direction; a gate extending along a second direction across the fin; and source/drain regions and a gate spacer on the fin at opposite sides of the gate, in which there is a surface layer on the top and/or sidewalls of the fin.