FinFET Switch Vertical Stacking for Low On-Resistance
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Solution Overview
Problem
As semiconductor device dimensions shrink, front-end-of-line (FEOL) and back-end-of-line (BEOL) resistances increase due to diffusion and shrinking metal conductor widths, respectively, making it challenging to achieve low on-resistance and high current ratio in finFET switches for power gating applications, which are essential for efficient power management in high-frequency chip operations.
Innovation Solution
The finFET switch structure incorporates a series of elongated fins and gates with a unique projection-based pattern that increases the fin contact area, eliminating fin-free areas and ensuring proper alignment of gate vias, resulting in lower on-resistance and enabling operation with lower supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimension shrinks, then integration density increases, but FEOL resistance rises due to diffusion and contact area decreases
Solution Approach 1:
The patent transitions from planar FinFET structures to vertically stacked 3D FinFET configurations, adding the vertical dimension to increase effective channel area and contact area without increasing lateral footprint. This dimensional change allows maintaining low resistance despite lateral scaling.
Solution Approach 2:
Multiple FinFET devices are stacked vertically within the same lateral footprint, creating a nested configuration where one device is placed above another. This nesting approach increases integration density while maintaining adequate contact area for each device through the vertical stacking arrangement.
2Quantity of substance
If device dimension shrinks, then integration density increases, but BEOL resistance rises due to shrinking metal conductor width and via size
Solution Approach 1:
The patent utilizes vertical stacking to route connections through the vertical dimension, reducing the lateral distance current must travel through high-resistance metal interconnects. This dimensional change mitigates BEOL resistance effects by shortening current paths in the scaled metal layers.
Solution Approach 2:
The patent divides the device into multiple stacked segments (FinFET devices) connected through vertical vias, allowing current to be distributed across multiple parallel paths. This segmentation reduces the effective resistance by providing multiple concurrent current flow paths despite individual via and conductor scaling.
3Ease of manufacture
If conventional FinFET structure is used, then manufacturing is simpler, but on-resistance is too high for efficient power gating
Solution Approach 1:
Multiple FinFET devices are stacked vertically to create a nested configuration that achieves low on-resistance through increased effective channel area. The nested stacking provides multiple parallel conduction paths while maintaining compatibility with existing manufacturing processes.
Solution Approach 2:
The patent moves from 2D planar FinFETs to 3D vertically stacked configurations, adding the vertical dimension to increase total channel area and reduce on-resistance. This dimensional transition maintains manufacturing feasibility while achieving the required electrical performance for power gating applications.
Data Source
AI summary
An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first direction and are spaced apart from each other in a second direction perpendicular to the first direction. The gates are interspersed between the contacts. The fins underlie both the contacts and the gates. The fins are elongated in the second direction and are spaced apart from each other in the first direction. A contact via extends through one of the contacts without contacting a gate or a fin. A gate via extends through one of the gates without contacting a contact or a fin. A contact-gate via is in contact with both a contact and a gate but not a fin.