FinFET T-Shaped Channel Etching for Higher Mobility Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in increasing integration density and mobility of electronic components due to limitations in feature size reduction and channel width in traditional transistor designs.
Innovation Solution
The formation of vertically stacked, self-aligned 'T' shaped channel regions through a self-limited etching process, which increases effective channel width and mobility by utilizing crystal directions, and is compatible with CMOS fabrication processes at a relatively low cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional transistor designs are used, then manufacturing simplicity is maintained, but integration density and mobility are limited
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional T-shaped and vertically stacked channel regions. This dimensional change increases the effective channel width and surface area without proportionally increasing the footprint area, thereby improving integration density while managing structural complexity through self-aligned fabrication processes
Solution Approach 2:
The channel region is segmented into multiple T-shaped or vertically stacked segments rather than a single continuous region. This segmentation increases the total effective channel width and allows for better control of carrier mobility by utilizing different crystal orientations in different segments, while the self-aligned process keeps manufacturing complexity manageable
2Productivity
If feature size is reduced to increase integration density, then more components fit in given area, but mobility and performance deteriorate
Solution Approach 1:
Instead of further reducing the lateral footprint dimensions, the patent extends the channel into the third dimension with T-shaped and vertically stacked structures. This maintains or reduces the footprint area for higher integration density while providing longer effective channel paths and multiple crystal orientations that enhance carrier mobility and device performance
Solution Approach 2:
Different portions of the channel region are engineered with different crystal orientations and geometries to optimize local carrier transport properties. The T-shaped and stacked structures create regions with favorable crystallographic orientations for high mobility, while maintaining overall compact dimensions for high integration density
3Reliability
If channel width is increased to improve mobility, then device area increases, but integration density decreases
Solution Approach 1:
The patent achieves increased effective channel width by extending the channel into the vertical dimension with stacked structures and T-shaped cross-sections. This provides larger effective channel area for improved carrier mobility while keeping the lateral footprint dimensions compact, thereby maintaining high integration density
Solution Approach 2:
Multiple channel regions are nested vertically in a stacked configuration, with each stack containing multiple T-shaped channel regions at different heights. This nesting approach consolidates multiple high-mobility channels into a compact vertical structure, improving mobility without increasing the lateral device footprint area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances mobility and integration density by optimizing channel dimensions and manufacturing compatibility, while maintaining cost-effectiveness.
Implementation Method 1
performing a self-limited anisotropic etching process to form T-shaped channel regions
Implementation Method 2
performing a self-limited solution based etching process to form T-shaped channel regions... performing a second etching process to form a second portion of the first recess... performing a third etching process to remove the first dielectric layer
Data Source
AI summary
A method includes etching a substrate to form a semiconductor fin, forming a gate stack on a top surface and sidewalls of the semiconductor fin, and forming a first recess in the semiconductor fin on a side of the gate stack, wherein forming the first recess comprises, performing a first etching process to form a first portion of the first recess, depositing a first dielectric layer on sidewalls of the gate stack and the first portion of the first recess, performing a second etching process to form a second portion of the first recess using the first dielectric layer as a mask, wherein the second portion of the first recess extends under the gate stack, and performing a third etching process to remove the first dielectric layer.