FinFET Fin Structure With T-Shaped Channels for Higher Current Density
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Solution Overview
Problem
The challenge in fabricating transistors at nanometer nodes lies in achieving efficient three-dimensional designs that minimize short channel effects and maximize current flow while maintaining device density and reducing fabrication costs, which existing finFET technologies struggle to address effectively.
Innovation Solution
The method involves forming semiconductor fins with alternating layers of different materials, selectively etching to create T-shaped cross-sections with wide and narrow portions, and conformally depositing a channel layer to enhance the effective width and current capacity of the transistors without increasing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistor designs are used, then fabrication is simpler, but device density and performance are limited
Solution Approach 1:
The patent transitions from planar (2D) transistor designs to three-dimensional finFET structures where the channel is formed on vertical fins extending perpendicular to the substrate. This dimensional change allows the gate to wrap-around and control the channel from multiple sides, significantly improving device density and performance while managing fabrication complexity through systematic process integration.
Solution Approach 2:
The transistor channel is segmented into multiple vertical fin structures rather than a single planar channel. Each fin acts as an independent channel region, allowing parallel current paths and increasing effective channel width without proportionally increasing footprint area, thereby enhancing device density.
2Productivity
If transistor size is reduced to increase device density, then more transistors fit on chip, but short channel effects increase and control becomes difficult
Solution Approach 1:
By transitioning to vertical fin structures, the patent achieves better gate control over the channel. The wrap-around gate configuration in finFETs provides electrostatic control from multiple sides of the channel, effectively suppressing short channel effects even as transistor dimensions are reduced to increase device density.
Solution Approach 2:
The patent employs alternating layers of different semiconductor materials (first and second semiconductor materials with different etch rates) to form the fin structure. This composite material approach enables selective etching processes that precisely define fin geometry and width, allowing accurate control of channel dimensions to mitigate short channel effects while maintaining high device density.
3Quantity of substance
If alternating layers of different semiconductor materials are used to form fins, then selective etching creates T-shaped cross-sections with increased effective width, but fabrication process complexity increases
Solution Approach 1:
The patent applies selective etching processes that target specific semiconductor material layers based on their different etch rates. The T-shaped cross-section is created by selectively removing portions of alternating material layers, allowing different regions of the fin structure to have different widths. This local quality variation increases effective channel width while managing fabrication complexity through material-specific process control.
Solution Approach 2:
The patent exploits differences in etch rate parameters between alternating semiconductor material layers to achieve selective removal and T-shaped cross-section formation. By controlling etch process parameters and exposure times, the fabrication process creates varied fin geometries with increased effective channel width without requiring fundamentally new fabrication techniques.
4Power
If fin width is increased to improve current carrying capacity, then more current flows, but chip area increases and device density decreases
Solution Approach 1:
The patent increases current carrying capacity by developing current flow in the vertical dimension through multiple fin structures extending perpendicular to the substrate. The wrap-around gate controls multiple vertical channel paths, allowing high total current capacity without increasing horizontal chip footprint, thus maintaining high device density while improving power handling capability.
Solution Approach 2:
The total current carrying capacity is distributed across multiple segmented fin structures rather than requiring a single large-width fin. Each fin contributes to the total current flow, and the segmented approach allows efficient use of vertical space to achieve high aggregate current capacity without proportionally increasing chip area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in increased transistor width and current carrying capacity, improving device performance and density while maintaining structural reliability and compatibility with standard CMOS processes.
Implementation Method 1
a selective etch is performed to remove portions of the alternating semiconductor layers based on different etch rates, resulting in T-shaped fin cross-sections
Implementation Method 2
channel layers are conformally deposited on the fins
Data Source
AI summary
A finFET device that includes a substrate and at least one semiconductor fin extending from the substrate. The fin may include a plurality of wide portions comprising a first semiconductor material and one or more narrow portions. The one or more narrow portions have a second width less than the first width of the wide portions. Each of the one or more narrow portions separates two of the plurality of wide portions from one another such that the plurality of wide portions and the one or more narrow portions are arranged alternatingly in a substantially vertical direction that is substantially perpendicular with a surface of the substrate. The fin may also include a channel layer covering sidewalls of the plurality of wide portions and a sidewall of the one or more narrow portions.