FinFET Channel Structure for Threshold Voltage Control at Short Gate Lengths
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Solution Overview
Problem
Current semiconductor devices with multi-gate transistors face challenges in scaling and controlling current without increasing gate length, and in suppressing short channel effects, while also requiring complex fabrication processes.
Innovation Solution
The semiconductor device incorporates fin-type active regions with different work function semiconductor material layers and gate lines, where the semiconductor material layer surrounds the gate lines and source/drain regions, allowing for independent control of threshold voltages across different areas of the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate transistors are used to improve current control capability and suppress short channel effects, then device performance is improved, but fabrication process complexity increases
Solution Approach 1:
The substrate is divided into first and second areas with different fin-type active region configurations. The first area has fins extending in a first direction while the second area has fins extending in a second direction perpendicular to the first direction. This segmentation allows different threshold voltage transistors to be formed in different areas through selective epitaxial growth, improving current control capability while managing fabrication complexity through regional differentiation.
Solution Approach 2:
Different regions of the substrate are given different local properties by controlling the orientation of fin-type active regions. The first area employs fins extending in one direction for a specific threshold voltage, while the second area employs fins extending in a perpendicular direction for a different threshold voltage. This local quality approach enables tailored current control characteristics in different device regions without requiring completely different fabrication processes.
2Reliability
If gate length is increased to improve current control capability, then current control is improved, but device area increases
Solution Approach 1:
Instead of increasing gate length in one dimension to improve current control, the invention utilizes the third dimension by forming three-dimensional fin-type active regions with channels extending vertically. The multi-gate structure wraps around the fin channel, providing superior current control through gate-all-around configuration without increasing the planar footprint of the device. This dimensional transition from 2D planar transistors to 3D finFETs enables enhanced current control with compact device area.
3Adaptability or versatility
If transistors with different threshold voltages are integrated on the same substrate, then device functionality is improved, but fabrication process complexity increases
Solution Approach 1:
The substrate is divided into distinct regions where fin-type active regions are oriented in different directions to create transistors with different threshold voltages. The first area contains fins extending in a first direction forming first threshold voltage transistors, while the second area contains fins extending in a perpendicular second direction forming second threshold voltage transistors. This local differentiation achieves diverse transistor characteristics on a single substrate while maintaining a unified fabrication process flow.
Solution Approach 2:
Fin-type active regions with different orientations are formed in different substrate areas before subsequent common processing steps. By pre-establishing the directional differences in fin orientation through selective epitaxial growth in different regions, the patent enables subsequent uniform processing to yield transistors with different threshold voltages, simplifying the overall fabrication process compared to post-processing differentiation methods.
Data Source
AI summary
Provided is a semiconductor device including a substrate, a fin-type active region protruding on the substrate, a channel region on the fin-type active region and including a plurality of active patterns extending in a first horizontal direction and a semiconductor material layer, a gate line extending in a second horizontal direction that is perpendicular to the first horizontal direction and covering the channel region on the fin-type active region, and a pair of source/drain regions at both sides of the gate line on the fin-type active region, wherein a work function of the semiconductor material layer is different from a work function of the plurality of active patterns, the semiconductor material layer surrounds portions of the gate line between the plurality of active patterns, and the gate line is separated from the pair of source/drain regions with the semiconductor material layer therebetween.