Fin-FET Threshold Voltage Tuning via Dummy Gate Ion Implantation
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Solution Overview
Problem
Existing semiconductor fabrication methods face challenges in maintaining desired electrical performance due to ion implantation losses during thermal oxidation processes, leading to deviations in threshold voltage tuning for Fin-FET devices.
Innovation Solution
A method involving the formation of dummy gate structures followed by ion implantation to tune threshold voltages after thermal oxidation, ensuring stability by avoiding ion loss and using a dielectric layer to level top surfaces of gate structures, thereby improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is performed during thermal oxidation process, then gate dielectric layer can be formed, but ion implantation losses occur leading to threshold voltage tuning deviations
Solution Approach 1:
The patent divides the fabrication process into separate stages: thermal oxidation is performed first to form the gate dielectric layer, then ion implantation is performed separately to tune the threshold voltage. This segmentation prevents ion loss that would occur if implantation were performed during oxidation, thereby improving threshold voltage tuning accuracy without sacrificing dielectric layer formation quality.
Solution Approach 2:
The gate dielectric layer is formed through thermal oxidation before the ion implantation step. This preliminary action ensures that the dielectric layer is already in place and stable before ions are implanted, preventing ion loss during oxidation while still achieving the desired threshold voltage tuning in the subsequent implantation step.
2Manufacturing precision
If dummy gate structures are formed before ion implantation, then threshold voltage tuning can be achieved, but process complexity increases
Solution Approach 1:
Dummy gate structures serve as intermediary elements that facilitate precise threshold voltage tuning during ion implantation. These temporary structures allow for accurate ion dosage control and threshold voltage adjustment, after which they are removed. The intermediary role of dummy gates enables precise control without permanently increasing device complexity.
Solution Approach 2:
The dummy gate structures are formed temporarily to enable precise ion implantation and threshold voltage tuning, then discarded in subsequent processing steps. This approach allows for high manufacturing precision during the critical implantation phase while avoiding permanent complexity in the final device structure, as the dummy gates are recovered (removed) after serving their purpose.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the stability and accuracy of threshold voltage tuning, reducing ion loss and improving electrical performance by separating ion implantation from thermal oxidation, ensuring consistent device performance.
Implementation Method 1
performing an ion implantation process on the first fin structures through each first dummy gate oxide layer to tune corresponding threshold voltages
Data Source
AI summary
A method for fabricating a semiconductor structure includes forming a plurality of first fin structures in a core region of a substrate and a plurality of second fin structures in a peripheral region of the substrate, forming a first dummy gate structure including a first dummy gate oxide layer and a first dummy gate electrode layer on each first fin structure and a second dummy gate structure including a second gate oxide layer and a second dummy gate electrode layer on each second fin structure. The method further includes removing each first dummy gate electrode layer, performing an ion implantation process to tune the threshold voltages of the first fin structures, and removing each first dummy gate oxide layer. The method also includes removing each second dummy gate electrode layer, and forming a gate dielectric layer and a metal layer on each first fin structure and each second fin structure.