FinFET Work-Function Layers With Tuned TiN Crystal Orientation
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Solution Overview
Problem
The semiconductor industry faces challenges in shrinking the size and increasing the speed of Fin Field-Effect Transistors (FinFETs) while maintaining effective work-function properties, as existing methods struggle to control the crystalline orientations and dopant diffusibility in work-function layers, affecting the threshold voltage and device performance.
Innovation Solution
The formation of work-function layers with specific proportions of crystalline orientations, such as (111) and (200) orientations in TiN, is achieved through controlled deposition processes, allowing for adjustable work-functions and dopant incorporation to optimize FinFET performance for both n-type and p-type transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of FinFETs is continuously shrunk to increase device density, then device density and integration capacity are improved, but control over work-function properties and threshold voltage becomes more difficult
Solution Approach 1:
The patent applies parameter changes by controlling the deposition conditions (temperature, pressure, precursor flow rates) to adjust the crystalline orientation proportions of TiN work-function material. By varying these deposition parameters, the work-function can be precisely tuned to achieve desired threshold voltages even in scaled-down FinFET devices, resolving the contradiction between device miniaturization and work-function control precision.
Solution Approach 2:
The patent uses composite material approaches by combining TiN with different crystalline orientations ((111) and (200) phases) in specific proportions within the same work-function layer. This composite structure allows independent optimization of work-function value and stability, enabling precise threshold voltage control in scaled devices while maintaining manufacturing feasibility.
2Ease of manufacture
If the crystalline orientation proportions in work-function layers are not controlled, then manufacturing process simplicity is maintained, but work-function suitability and device performance deteriorate
Solution Approach 1:
The patent implements preliminary action by establishing optimized deposition parameter ranges before actual device fabrication. By pre-determining the temperature, pressure, and precursor ratios that yield desired crystalline orientation proportions, the process becomes routine and manufacturable while ensuring consistent work-function properties and device performance across production batches.
Solution Approach 2:
The patent systematically varies deposition parameters (temperature between 200-400°C, pressure, precursor flow rates) to achieve target crystalline orientation ratios. This parameter optimization creates a robust process that balances manufacturing ease with reliable device performance, as the optimized parameters can be consistently reproduced in production environments.
3Device complexity
If dopant diffusibility in work-function layers is not controlled, then process complexity is reduced, but threshold voltage control and device speed deteriorate
Solution Approach 1:
The patent applies local quality by creating regions with different crystalline orientations within the work-function layer. The (111) orientation provides lower dopant diffusibility for stable threshold voltage, while the (200) orientation offers higher diffusibility for faster carrier transport. This spatial differentiation of material properties within the same layer enables simultaneous optimization of device speed and threshold voltage control without increasing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control over the threshold voltage and work-function suitability of FinFETs, enhancing process flexibility and device performance by adjusting the crystalline orientation proportions and dopant concentrations in the work-function layers.
Implementation Method 1
depositing a work-function material using a first set of process parameters, wherein the first set of process parameters is associated with forming the work-function material having a first work-function
Implementation Method 2
the first work-function is associated with a first proportion of a first crystalline orientation and a second crystalline orientation of the work-function material
Implementation Method 3
a first diffusibility of the dopant and the second crystalline orientation has a second diffusibility of the dopant that is different from the first diffusibility
Data Source
AI summary
A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.