Ultra-Thin Body FinFET With U-Shaped Trench Gate
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Solution Overview
Problem
Existing FinFET devices face challenges in achieving optimal performance due to issues such as short channel effects, high leakage current, and difficulties in controlling the thickness of the channel region, which affect device density and efficiency.
Innovation Solution
A FinFET device structure with an ultra-thin body is formed by creating a U-shaped trench in a semiconductor layer, dividing it into source, channel, and drain structures, and using a gate structure within the trench, where the channel region has a controlled thickness of 1-20 nm, achieved through dry etching to minimize variations and enhance control over leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional FinFET fabrication methods are used, then device density is improved, but short channel effects and leakage current increase
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional FinFET structures with vertical channels extending from the substrate. This dimensional change increases the effective channel area and device density while maintaining short channel effect control through the vertical fin geometry that provides better gate electrostatic control.
Solution Approach 2:
The patent applies different material compositions and doping concentrations to specific regions of the FinFET structure. The channel region has optimized doping levels compared to source and drain regions, and the gate dielectric layer uses high-k materials in specific areas to enhance local electrostatic control and reduce leakage current in critical regions.
2Reliability
If channel thickness is reduced to control short channel effects, then leakage current decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces a gate dielectric layer as an intermediary between the gate electrode and the ultra-thin channel region. This dielectric layer with high-k material properties provides enhanced electrostatic control over the channel, enabling effective leakage current suppression even when the channel thickness is reduced to 1-20 nm, while relaxing the precision requirements for channel thickness control.
3Reliability
If ultra-thin channel region is formed, then Ion/Ioff ratio improves, but fabrication complexity increases
Solution Approach 1:
The patent performs preliminary actions by pre-forming the fin structures with appropriate dimensions and doping profiles before creating the ultra-thin channel region. The source and drain regions are pre-doped with optimized concentrations, and the gate dielectric is pre-deposited with high-k materials, which simplifies the subsequent channel formation process and reduces overall fabrication complexity despite the ultra-thin channel requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ultra-thin body FinFET device structure achieves improved performance with high Ion/Ioff current, low drain-induced barrier lowering, low subthreshold swing, high saturation current, high electron density, and fast electron velocity, while minimizing short channel effects and leakage current.
Implementation Method 1
achieved through dry etching to minimize variations and enhance control over leakage current
Data Source
AI summary
A method for forming a semiconductor device structure is provided that includes forming an oxide layer over a substrate and forming a semiconductor layer over the oxide layer. The method includes patterning the semiconductor layer to form a fin structure over the oxide layer and removing a portion of the fin structure to form a U-shaped trench in the fin structure. The method also includes forming a gate structure on the U-shaped trench.