FinFET Under-Spacer Doping for Resistance-Capacitance Tradeoff
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Solution Overview
Problem
Fin-based semiconductor devices face a tradeoff where lowering extension resistance through thicker epitaxial layers increases parasitic capacitance, necessitating a decoupling of these two components.
Innovation Solution
The implementation of a fin field effect transistor (FinFET) device with an epitaxial layer formed between the fin and a spacer, allowing for a thicker epitaxial layer in the extension region while maintaining a thinner layer in the channel region, thereby reducing extension resistance without increasing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the epitaxial layer is thickened to lower extension resistance, then extension resistance decreases, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by forming a thicker epitaxial layer specifically in the extension region (under the spacer) while maintaining a thinner epitaxial layer in the channel region. This spatial differentiation allows the extension region to have low resistance (thick layer) while the channel region maintains low capacitance (thin layer), thereby resolving the contradiction between extension resistance and parasitic capacitance.
2Reliability
If the epitaxial layer is thickened to reduce extension resistance, then extension resistance decreases, but capacitor area increases
Solution Approach 1:
The invention implements local quality by creating a non-uniform epitaxial layer thickness profile: thick under the spacer in the extension region to reduce resistance, and thin over the channel region to minimize capacitor area. This localized thickness control allows independent optimization of resistance and capacitance characteristics in different functional regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively lowers extension resistance while keeping parasitic capacitance low, addressing the tradeoff challenge in fin-based semiconductor devices.
Implementation Method 1
an epitaxial layer formed over portions of the fin, the epitaxial layer being included between the fin and the spacer
Data Source
AI summary
A fin field effect transistor (FinFET) device and a method of fabricating the FinFET are described. The device includes a fin formed on a substrate, the fin including a channel region of the device and a spacer and a cap formed over a dummy gate line separating a source and drain of the device. The device also includes an epitaxial layer formed over portions of the fin, the epitaxial layer being included between the fin and the spacer.