FinFET Unmerged Source Drain Epitaxy via Dielectric Confinement
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Solution Overview
Problem
In semiconductor manufacturing, existing technologies face challenges in forming wide unmerged epitaxially grown source drain regions for FinFET devices, which are crucial for advanced integrated circuits, as they often result in adjacent source drain regions merging, leading to electrical shorts and limiting device density and performance.
Innovation Solution
A method involving the formation of fin spacers on semiconductor fins, followed by recessing and selective removal to create openings for epitaxial growth, where the growth is constrained by a dielectric layer, allowing for the formation of unmerged source drain regions with a diamond-shaped cross-section, preventing lateral merging and optimizing fin spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional epitaxial growth methods are used to form source drain regions, then the source drain regions can be formed, but adjacent source drain regions merge together causing electrical shorts
Solution Approach 1:
A dielectric layer is introduced as an intermediary barrier between adjacent source drain regions during epitaxial growth. This dielectric layer physically prevents lateral merging of the source drain regions while allowing vertical growth, thereby maintaining electrical isolation and preventing shorts between adjacent devices
Solution Approach 2:
The source drain region formation process is segmented into controlled stages with the dielectric layer acting as a segmentation barrier. The epitaxial growth is confined to specific regions by the dielectric layer, creating discrete separated source drain regions rather than continuous merged structures
2Productivity
If fin spacing is reduced to increase device density, then more devices can be packed, but adjacent source drain regions are more likely to merge
Solution Approach 1:
The dielectric layer acts as a mediator that enables reduced fin spacing by preventing lateral epitaxial growth between adjacent fins. This allows devices to be packed more densely while the dielectric layer maintains electrical isolation between closely spaced source drain regions
Solution Approach 2:
The solution moves the isolation function from the lateral dimension to the vertical dimension by introducing the dielectric layer in the vertical stack. This allows lateral fin spacing to be reduced while vertical dielectric confinement prevents merging
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of larger volume source drain regions without merging, enhancing device performance by increasing channel strain and source/drain doping, while maintaining optimal fin spacing and device density, thus supporting the fabrication of advanced semiconductor devices.
Implementation Method 1
forming an unmerged source drain region in the second opening by epitaxially growing a semiconductor material from an exposed surface of a remaining portion of the fin
Data Source
AI summary
A method including forming fin spacers on opposite sidewalls of a semiconductor fin made from a semiconductor substrate, forming a dielectric layer in direct contact with the fin spacers such that a top surface of the fin and a top surface of the fin spacers remain exposed, recessing a portion of the fin between the fin spacers, removing the fin spacers to create an opening, and epitaxially growing an unmerged source drain region in the opening, where lateral growth of the unmerged source drain region is constrained on opposite sides by the dielectric layer.