FinFET Channel Epitaxy Under Vacuum for Ge Diffusion Control
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing fin field effect transistors (Fin FETs) with high aspect ratio semiconductor fins, where channel and source/drain regions are formed, due to difficulties in controlling the dimensions and material properties of the fin structures, leading to issues with electrical isolation and Ge diffusion.
Innovation Solution
A method involving sequential dielectric layer formation and chemical dry etching is used to create fin structures with precise dimensions, followed by epitaxial growth of a cap semiconductor layer to control Ge diffusion and electrical properties, with operations performed in a single chamber to maintain vacuum and optimize conditions for selective etching and growth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing methods are used for Fin FETs, then production can proceed with standard processes, but manufacturing precision of fin structures deteriorates due to difficulties in controlling dimensions and material properties
Solution Approach 1:
The manufacturing process is divided into distinct sequential steps: forming first dielectric layer, forming second dielectric layer, chemical dry etching to create fin structures, and epitaxial growth of cap semiconductor layer. Each step is optimized independently to achieve precise fin structure dimensions while managing overall process complexity.
Solution Approach 2:
The patent employs chemical dry etching with controlled parameters (gas composition, power, pressure, temperature) to precisely define fin structure dimensions. Epitaxial growth parameters (temperature, pressure, gas flow rates) are also carefully controlled to manage Ge diffusion and achieve desired material properties, thereby improving manufacturing precision.
2Reliability
If epitaxial growth is performed after cleaning in separate chambers, then each process can be optimized independently, but Ge diffusion control deteriorates due to exposure to ambient conditions
Solution Approach 1:
The cleaning operation and epitaxial growth are merged into a single vacuum chamber, allowing the channel region to be cleaned and immediately capped with the epitaxial semiconductor layer without exposure to ambient conditions. This prevents Ge diffusion while maintaining independent process optimization through sequential operation within the same chamber.
Solution Approach 2:
The process maintains continuous vacuum conditions from cleaning through epitaxial growth, eliminating breaks that would expose the channel region to ambient atmosphere. The useful action of Ge diffusion prevention continues uninterrupted throughout the sequence, improving reliability while the single-chamber design manages integration complexity.
3Productivity
If high aspect ratio fin structures are formed, then device density increases, but electrical isolation deteriorates due to difficulties in controlling fin structure dimensions
Solution Approach 1:
Different dielectric layers are used at different locations: the first dielectric layer fills spaces between fin structures for electrical isolation, while the second dielectric layer provides a planarization layer for subsequent processing. This local differentiation allows high aspect ratio fins for density while maintaining proper electrical isolation through the first dielectric layer.
Solution Approach 2:
The patent uses vertical stacking of multiple dielectric layers to solve the isolation problem. The first dielectric layer is positioned laterally between fins for isolation, while the second dielectric layer extends vertically to provide planarization and support, allowing high aspect ratio fins without compromising electrical isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses Ge diffusion and improves electrical properties by forming fin structures with precise dimensions and controlled epitaxial layers, enhancing the performance and reliability of Fin FETs.
Implementation Method 1
A cleaning operation is performed and an epitaxial semiconductor layer is formed over the channel region. In one embodiment, the cleaning operation is a chemical dry etching using a mixed gas of HF, NH3 and N2.
Implementation Method 2
an epitaxial semiconductor layer is formed over the channel region
Data Source
AI summary
In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.