FinFET Fin Patterning With Variable Spacing for Mixed Fin Counts
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Solution Overview
Problem
Current fin patterning techniques for integrated circuits (ICs) face challenges in achieving both high precision and flexibility in forming odd and even numbers of fin lines, particularly at advanced technology nodes, where tighter fin pitches and smaller geometries complicate the fin cutting process, leading to limitations in process margins and fin profile uniformity.
Innovation Solution
The proposed method involves a hybrid approach combining spacer lithography with a fin cut last process, where a dummy pattern with varying widths is used to form spacers with different spacings in different regions, allowing for the formation of both single-fin and multi-fin FinFETs with improved lithography overlay margins and vertical fin profiles, enabling the fabrication of ICs with both high speed and low power consumption capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple patterning processes are used to meet shrinking fin widths and fin pitches, then fin width and pitch precision is improved, but the fin cutting process becomes more complex and process margins are significantly limited
Solution Approach 1:
The fin patterning process is segmented into multiple stages: initial fin formation using spacer lithography, followed by selective fin removal in specific regions. This segmentation allows the complex task of creating different fin numbers in different regions to be broken down into manageable steps, each with optimized process margins
Solution Approach 2:
The dummy fin structures are formed in advance during the spacer lithography process, before the actual fin cutting is performed. These dummy fins serve as placeholders that guide subsequent selective removal processes, ensuring that the final fin configurations (odd or even numbers) are achieved with proper alignment and spacing
2Adaptability or versatility
If fin cutting process is used to provide odd number of fin lines, then different fin numbers in different regions is achieved, but process margins are significantly limited
Solution Approach 1:
Dummy fin structures serve as intermediary elements that facilitate the creation of odd-numbered fin configurations. These dummy fins are formed using spacer lithography with controlled spacing, then selectively removed in specific regions to leave the desired odd number of fins, thereby mediating between the spacer lithography process and the final fin structure
Solution Approach 2:
The fin structure is designed with different local characteristics: regions requiring odd numbers of fins include dummy fins during intermediate stages, while regions requiring even numbers maintain the full spacer-formed structure. This local differentiation allows each region to be optimized for its specific fin number requirement while using the same overall fabrication approach
3Quantity of substance
If tighter fin pitches are used for advanced IC technology nodes, then functional density is increased, but fin profile uniformity and process margins deteriorate
Solution Approach 1:
The spacer lithography process is self-aligning: spacers are formed conformally on sacrificial structures, and their positions are automatically determined by the spacer thickness and the sacrificial structure geometry. This self-service mechanism ensures uniform fin profiles and consistent spacing even at tight pitches, as the process inherently compensates for variations
Data Source
AI summary
Fin patterning methods disclosed herein achieve advantages of fin cut first techniques and fin cut last techniques while providing different numbers of fins in different IC regions. An exemplary method implements a spacer lithography technique that forms a fin pattern that includes a first fin line and a second fin line in a substrate. The first fin line and the second fin line have a first spacing in a first region corresponding with a single-fin FinFET and a second spacing in a second region corresponding with a multi-fin FinFET. The first spacing is greater than the second spacing, relaxing process margins during a fin cut last process, which partially removes a portion of the second line in the second region to form a dummy fin tip in the second region. Spacing between the dummy fin tip and the first fin in the second region is greater than the second spacing.