FinFETs with Variable Fin Height for Device Width Control
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Solution Overview
Problem
Conventional FinFETs have limited control over device width, which restricts the optimization of aspect ratios and performance in integrated circuits, particularly in applications like static random access memory where precise width ratios between P-channel and N-channel FETs are required.
Innovation Solution
The integration of FinFET devices with fins of different heights, achieved through a method involving the formation of a shallow trench isolation layer, selective oxidation, and epitaxial layer deposition, allows for more precise control of transistor aspect ratios by varying the height of the fins, enabling adjustable device width beyond traditional quantized limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional FinFET structures with uniform fin heights are used, then manufacturing simplicity is maintained, but device width control is limited to quantized values only
Solution Approach 1:
The fin structure is segmented into multiple sections with different heights along its length. Each section can have a different height, allowing the effective device width to be controlled by selecting which sections are active. This segmentation enables continuous device width control rather than quantized values, resolving the contradiction between manufacturing precision and device complexity.
Solution Approach 2:
The invention introduces height as an additional dimension for controlling device characteristics. Instead of only varying device width in the planar direction, the fin height is varied in the vertical dimension to achieve continuous control over effective device width. This dimensional approach allows precise device width control while maintaining relatively simple manufacturing processes.
2Manufacturing precision
If multiple fins are added or deleted to adjust device width, then device width can be changed in quantized steps, but precise aspect ratio control is not achieved
Solution Approach 1:
The fin structure is made dynamic by allowing different sections to have different heights. This enables continuous adjustment of the effective device width by selecting which fin sections are active, rather than being limited to fixed quantized steps. The dynamic height variation allows precise aspect ratio control for optimized circuit performance while maintaining fabrication efficiency.
3Productivity
If channel length is reduced to improve performance, then device density increases, but short channel effects degrade threshold behavior
Solution Approach 1:
Different sections of the fin have different heights, creating local variations in the electric field distribution along the channel. This local quality variation allows for better control of short channel effects in specific regions while maintaining high device density. The varied fin heights provide enhanced gate control over the channel, improving threshold behavior despite reduced channel length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more precise control over transistor aspect ratios, enhancing integration applications by allowing for optimized performance in various circuit configurations, such as static random access memory, by adjusting the height of fins in FinFETs.
Implementation Method 1
Selective oxidation is performed to convert the SiGe layer of each fin into an oxide layer
Implementation Method 2
Source and drain epitaxy is then performed
Data Source
AI summary
A method of forming a semiconductor circuit having FinFET devices that have fins of different height is provided. There is a shallow trench isolation layer (STI) on top of a semiconductor substrate. A first Fin Field Effect Transistor (FinFET) comprises a first semiconductor fin including a first layer that extends from a common substrate level through the STI layer to a first height above a top surface of the STI layer. There is a second FinFET comprising a second semiconductor fin including the first layer that extends from the common substrate level through the STI layer to the first height above the top surface of the STI layer, plus a second layer having a second height, plus a third layer having a third height. The second semiconductor fin is taller than the first semiconductor fin.