FinFET and vFET Substrate Layout for Gate Length Control
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Solution Overview
Problem
The existing semiconductor device manufacturing processes face challenges in effectively forming finFET and vFET structures on the same substrate, particularly in achieving precise gate structure alignment and minimizing the variation in gate lengths, which affects the electrical characteristics of the transistors.
Innovation Solution
The semiconductor device is designed with a substrate having distinct regions for finFET and vFET, where the finFET includes a semiconductor pattern protruding vertically with a gate structure covering its surface and sidewall, and the vFET has a semiconductor pattern protruding vertically with a gate structure covering its sidewall, along with source/drain layers, allowing for precise control of transistor structures and minimizing gate length variation through specific etching and spacer formation processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a gate of the vFET exposes an upper portion of a semiconductor pattern, then the gate structure can be formed, but the insulating interlayer must be etched to expose a hard mask, increasing process complexity
Solution Approach 1:
The patent applies preliminary action by forming the insulating interlayer to a greater thickness in the vFET region before gate formation. This pre-positioned thicker insulating layer serves as a built-in mask that prevents the gate etch from exposing the semiconductor pattern, eliminating the need for additional hard mask formation and reducing process complexity.
Solution Approach 2:
The patent uses the insulating interlayer as an intermediary element between the gate and the semiconductor pattern. By controlling the thickness of this interlayer, it mediates the etching process to prevent direct exposure of the semiconductor pattern, thereby simplifying the overall manufacturing process.
2Adaptability or versatility
If finFET and vFET are formed on the same substrate, then device integration is achieved, but gate length variation increases affecting electrical characteristics
Solution Approach 1:
The patent applies local quality by forming the insulating interlayer with different thicknesses in different regions of the substrate. The vFET region receives a thicker insulating layer while the finFET region receives a standard thickness. This localized differentiation allows each transistor type to have optimized gate length control tailored to its specific requirements, enabling precise manufacturing despite device integration.
Solution Approach 2:
The patent segments the substrate into distinct regions (finFET region and vFET region) with different insulating interlayer thicknesses. This segmentation allows independent optimization of gate formation processes for each transistor type, preventing gate length variation that would otherwise occur in a uniform structure.
3Ease of manufacture
If the upper surface of the first region is lower than the upper surface of the second region, then selective etching is enabled, but additional substrate processing steps are required
Solution Approach 1:
The patent applies preliminary action by selectively removing portions of the substrate to create regions with different upper surfaces at an early stage. This pre-created height difference in the substrate enables subsequent selective etching processes to naturally target specific regions without requiring complex masking or alignment steps, simplifying the overall manufacturing approach.
Data Source
AI summary
A semiconductor device including a substrate including first and second regions, a first transistor on the first region and including a first semiconductor pattern protruding from the first region; a first gate structure covering an upper surface and sidewall of the first semiconductor pattern; first source/drain layers on the first semiconductor pattern at opposite sides of the first gate structure, upper surfaces of the first source/drain layers being closer to the substrate than an uppermost surface of the first gate structure; and a second transistor on the second region and including a second semiconductor pattern protruding from the second region; a second gate structure covering a sidewall of the second semiconductor pattern; and a second source/drain layer under the second semiconductor pattern; and a third source/drain layer on the second semiconductor pattern, wherein the upper surface of the first region is lower than the upper surface of the second region.