FinFET Void Isolation Structure for Gate Leakage and Capacitance
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area with reduced minimum feature sizes, issues such as increased capacitance and current leakage between gate electrodes and source/drain regions become significant challenges.
Innovation Solution
The formation of voids in FinFETs by removing one of the gate spacers, which are then filled with low relative permittivity materials, reduces capacitance and minimizes current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If gate spacers are removed to form voids, then capacitance and current leakage are reduced, but device complexity increases
Solution Approach 1:
One of the gate spacers is selectively removed to form a void region, extracting the problematic dielectric material that causes capacitance and current leakage. This targeted removal reduces the harmful electrical interactions between gate electrodes and source/drain regions while maintaining the structural integrity of the FinFET device.
Solution Approach 2:
The void formed by removing the gate spacer creates a porous or empty space that is then filled with low relative permittivity material. This porous structure approach allows for reduced capacitance by introducing air or vacuum spaces, or by using materials with deliberately low dielectric constants in critical regions.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components are integrated into a given area, but capacitance and current leakage increase
Solution Approach 1:
The patent applies different dielectric quality characteristics to different regions of the device. Specifically, low relative permittivity material is used in the void region between gate electrodes and source/drain contacts, while other regions may use conventional dielectric materials. This local differentiation allows reduced capacitance and current leakage in critical areas without compromising overall device functionality.
Solution Approach 2:
The relative permittivity parameter of the dielectric material is changed in specific regions by using low relative permittivity materials in the void spaces. This parameter change directly reduces the capacitance between gate electrodes and source/drain regions, addressing the current leakage issue that arises from reduced minimum feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively decreases capacitance and current leakage, enhancing the performance and efficiency of FinFETs by maintaining low relative permittivity between gate electrodes and source/drain regions.
Implementation Method 1
decreases capacitance and current leakage, enhancing the performance and efficiency of FinFETs by maintaining low relative permittivity between gate electrodes and source/drain regions
Data Source
AI summary
In an embodiment, a device includes: a first fin extending from a substrate; a gate stack disposed on the first fin; a source/drain region disposed in the first fin; a contact etch stop layer (CESL) disposed over the source/drain region; a gate spacer extending along a side of the gate stack; and a dielectric plug disposed between the CESL and the gate spacer, where the dielectric plug, the CESL, the gate spacer, and the source/drain region collectively define a void physically separating the gate stack from the source/drain region.