FinFET Void Spacer Structure for Lower Gate-to-Drain Capacitance
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, they face challenges such as increased current leakage due to high capacitance between gate electrodes and source/drain regions, which existing technologies have not adequately addressed.
Innovation Solution
The formation of voids between gate electrodes and source/drain regions by removing a gate spacer, which are then filled with air or vacuum, reducing the relative permittivity and thereby minimizing capacitance and current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional fabrication processes are used with solid dielectric materials, then manufacturing is straightforward, but capacitance between gate electrodes and source/drain regions remains high causing increased current leakage
Solution Approach 1:
The patent removes a portion of the gate spacer to form a void between the gate electrode and source/drain regions. This extraction of material creates an air-filled or vacuum-filled space that replaces the solid dielectric, thereby reducing capacitance and current leakage while maintaining the basic fabrication workflow
Solution Approach 2:
The patent changes the physical state of the dielectric medium from solid (conventional dielectric material) to gas/vacuum (air or vacuum in the void). This parameter change fundamentally reduces the permittivity and capacitance between gate and source/drain regions, addressing the energy loss issue
2Productivity
If feature sizes are reduced to increase integration density, then more components fit in a given area, but capacitance effects and current leakage increase
Solution Approach 1:
The patent applies local quality by creating voids specifically in the regions between gate electrodes and source/drain contacts where capacitance causes problems. The rest of the device maintains conventional solid dielectric structures, allowing integration density improvements while locally reducing energy loss through the air/vacuum-filled voids
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces capacitance and current leakage in FinFETs, enhancing the performance of semiconductor devices by creating a low-permittivity environment between the gate electrodes and source/drain regions.
Implementation Method 1
The voids may be filled with air or may be at a vacuum, such that regions between the gate electrodes and source/drain regions of the FinFET can have a low relative permittivity. The capacitance between the gate electrodes and source/drain contacts of the FinFET may thus be reduced
Data Source
AI summary
A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.