FinFET Void Spacer Structure for Gate Leakage Reduction
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the increasing capacitance between gate electrodes and source/drain regions due to the high permittivity of dielectric materials leads to significant current leakage, which affects the integration density and performance of FinFETs.
Innovation Solution
The formation of voids between gate electrodes and source/drain regions by removing a gate spacer, which are then filled with air or vacuum, reduces the relative permittivity and thereby decreases the capacitance, mitigating current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric materials with high permittivity are used to fill the space between gate electrodes and source/drain regions, then the capacitance is increased, but current leakage increases significantly
Solution Approach 1:
The patent removes the gate spacer material from the space between the gate electrode and source/drain regions, creating a void. This extraction of the dielectric material eliminates the source of high capacitance that causes current leakage, directly resolving the technical contradiction by taking out the harmful element rather than replacing it with a beneficial one.
Solution Approach 2:
The patent changes the permittivity parameter of the material in the space between gate and source/drain from high (dielectric material) to low (air or vacuum). By changing this physical parameter, the capacitance is reduced, thereby reducing current leakage while maintaining the electrical isolation function.
2Productivity
If feature sizes are reduced to increase integration density, then more components can be integrated, but capacitance and current leakage problems worsen
Solution Approach 1:
The patent applies local quality by creating a void specifically in the region between the gate electrode and source/drain regions, while leaving other areas unchanged. This localized modification reduces capacitance and current leakage in the critical area without affecting the overall miniaturization and integration density achievements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces current leakage and enhances the performance of FinFETs by lowering the capacitance between gate electrodes and source/drain regions, improving the integration density and overall device performance.
Implementation Method 1
reduces the relative permittivity and thereby decreases the capacitance
Data Source
AI summary
A method for making a semiconductor device includes: forming a first gate stack over a first fin; forming a first gate spacer extending along a side of the first gate stack; forming a second gate spacer over the first gate spacer; forming a third gate spacer over the second gate spacer, the third gate spacer; forming a source/drain region adjacent the third gate spacer; depositing an interlayer dielectric (ILD) over the source/drain region, the ILD including a third dielectric material; and removing at least a portion of the second gate spacer to form a void, while exposing a top surface of the ILD. The void includes a vertical portion extending between the first gate spacer and the source/drain region, and between the first gate spacer and the ILD. The void includes a horizontal portion extending beneath the source/drain region.