FinFET Wall Fin Structure for Source/Drain Epitaxy Separation
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Solution Overview
Problem
In the manufacturing of fin field effect transistors (Fin FETs), the shape of the epitaxial source/drain structure significantly affects device performance, but existing methods struggle to define optimal shapes, particularly when adjacent fin structures are close, leading to undesired merging of epitaxial layers.
Innovation Solution
The use of a wall fin structure, comprising a dielectric dummy fin, to physically and electrically separate adjacent source/drain epitaxial layers and define their shape, thereby improving the Ion/Ioff current ratio and overall device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If adjacent fin structures are placed close together to increase device density, then productivity and device density are improved, but the epitaxial source/drain layers may undesirably merge leading to loss of manufacturing precision
Solution Approach 1:
A dielectric wall fin structure is introduced as an intermediary element between adjacent semiconductor fins. This wall fin physically separates the fins and prevents merging of epitaxial source/drain layers during fabrication, while allowing the fins to remain closely spaced for high device density. The wall fin acts as a mediator that enables both high density and precise layer separation.
Solution Approach 2:
The space between adjacent semiconductor fins is segmented by introducing a dielectric wall fin structure. This segmentation creates distinct isolation regions that prevent interaction between adjacent epitaxial layers, enabling each fin to be processed independently while maintaining close spacing for high device density.
2Manufacturing precision
If a wall fin structure is introduced to separate epitaxial layers, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The dielectric wall fin structure serves multiple functions simultaneously: it acts as a physical barrier to prevent epitaxial layer merging, provides electrical isolation between adjacent fins, and serves as a structural template during fabrication. This multi-functionality reduces the need for additional separate structures, thereby limiting the increase in device complexity.
Solution Approach 2:
The wall fin structure combines several functions into a single element: physical separation, electrical isolation, and fabrication template. By merging these functions into one structure rather than using multiple separate components, the increase in device complexity is minimized while still achieving precise epitaxial layer separation.
Data Source
AI summary
In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.