Dielectric Wall Fin Layout for FinFET Source/Drain Shape Control

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Solution Overview

Problem

In FinFET devices, the epitaxial source/drain structure shape significantly affects device performance, and existing methods struggle to maintain optimal shape and separate adjacent epitaxial layers, leading to undesired merging and reduced Ion/Ioff current ratios.

Innovation Solution

A wall fin structure using dielectric dummy fins is employed to physically and electrically separate adjacent source/drain epitaxial layers, defining their shape and improving the FinFET's Ion/Ioff current ratio through a sequential manufacturing process involving multiple dielectric layers and etching operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional manufacturing methods are used to form source/drain epitaxial layers, then the manufacturing process is simple, but adjacent epitaxial layers merge and device performance deteriorates

Engineering Contradiction:
Improvedevice performanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A dielectric wall fin structure is introduced as an intermediary element between adjacent semiconductor fins. This wall fin physically separates the source/drain regions of neighboring fins during epitaxial growth, preventing merging of epitaxial layers while maintaining manufacturing feasibility through sequential deposition and etching processes

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The continuous dielectric layer is segmented into discrete wall fin structures positioned between adjacent semiconductor fins. This segmentation creates individual separation zones for each fin, enabling independent control of epitaxial layer formation and preventing unwanted merging while preserving the overall device architecture

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If no separation structure is used, then the manufacturing process is simpler, but adjacent source/drain epitaxial layers merge leading to reduced Ion/Ioff current ratios

Engineering Contradiction:
Improveepitaxial layer shape controlVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The dielectric wall fin acts as a mediator that defines the boundary between adjacent source/drain regions. During epitaxial growth, the wall fin serves as a physical barrier that stops lateral expansion of epitaxial material, precisely controlling the shape and dimensions of source/drain layers without requiring complex lithographic patterning

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric wall fin structure is formed in advance before source/drain epitaxial growth. This preliminary action pre-establishes the separation boundaries and shape constraints, allowing subsequent epitaxial layers to grow with controlled morphology without requiring additional shaping steps

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11830937B2Method of manufacturing a semiconductor device and a semiconductor device
Publication Date: 2023.11.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11830937B2 patent drawing
  • US11830937B2 patent drawing
  • US11830937B2 patent drawing

AI summary

In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.