FinFET Well and Fin Structure for Leakage Current Isolation
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Solution Overview
Problem
The challenge in the semiconductor industry is to form reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, affecting production efficiency and costs.
Innovation Solution
The formation of a semiconductor device structure using FinFETs, where fins are patterned using photolithography and self-aligned processes, with sacrificial layers, spacers, and epitaxial structures, and the creation of well regions and gate stacks to improve device performance and reduce leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple sequential stages including forming first and second trenches at different depths, selective epitaxial growth in specific regions, and staged doping processes. This segmentation allows complex device structures to be built through manageable, modular steps that can be precisely controlled at each stage.
Solution Approach 2:
The method performs preliminary actions by pre-forming isolation trenches and defining active regions before proceeding with device formation. The first trench is created and filled with isolation material in advance, and selective regions are prepared with different epitaxial structures beforehand, which simplifies subsequent processing steps and improves overall fabrication efficiency.
2Area of stationary object
If feature sizes continue to decrease, then more devices fit per chip area, but reliability of device formation becomes more difficult to achieve
Solution Approach 1:
Isolation structures (shallow trench isolation and deep trench isolation) are introduced as intermediary elements that electrically separate different device regions. These isolation trenches act as mediators that prevent unwanted electrical interactions between adjacent devices, thereby improving device formation reliability while enabling higher density integration on the chip.
Solution Approach 2:
The patent applies different epitaxial structures and doping conditions to specific local regions of the substrate. Selective regions receive different treatments (e.g., n-type vs p-type epitaxial growth, different doping concentrations) tailored to their specific functional requirements, which ensures reliable device operation in each region while maintaining overall high-density integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of semiconductor devices by reducing leakage current, allowing for more efficient production and potentially lowering costs by simplifying the process and improving temperature sensing accuracy in devices like CPUs and GPUs.
Implementation Method 1
fins are patterned using photolithography and self-aligned processes
Implementation Method 2
epitaxial structures
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes forming a first well region and a second well region in a substrate. The method includes forming a third well region in the substrate and between the first well region and the second well region. The method includes forming a deep well region in the substrate and under the first well region and the third well region. The method includes partially removing the substrate to form a first fin, a second fin, and a third fin in the first well region, the second well region, and the third well region respectively. The method includes forming a first epitaxial structure, a second epitaxial structure, and a third epitaxial structure in the first recess, the second recess, and the third recess respectively.