FinFET Well Isolation Structure for SRAM Latch-Up Suppression

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Solution Overview

Problem

Leakage current between oppositely doped well regions in FinFETs, particularly in SRAM designs, leads to latch-up issues due to positive feedback causing circuit failure.

Innovation Solution

Implement well isolation features by forming dielectric-filled recesses between N-type and P-type well regions, reducing the flow of leakage current through these regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device spacing is reduced to increase functional density, then productivity increases, but leakage current between well regions increases causing latch-up

Engineering Contradiction:
Improvefunctional densityVSAvoidleakage current
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

By segmenting the continuous substrate into isolated well regions with dielectric material, the patent enables closer device spacing without increasing leakage current. The segmentation creates electrical isolation that prevents harmful current paths even when devices are densely packed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dielectric material serves as an intermediary barrier that allows reduced device spacing while maintaining electrical isolation. This intermediary layer prevents leakage current from increasing even as functional density increases through closer device placement.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If well isolation features are added to prevent latch-up, then reliability improves, but device complexity increases

Engineering Contradiction:
Improvelatch-up preventionVSAvoidfabrication complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dielectric material layer serves multiple functions: it provides well isolation to prevent latch-up, acts as a planarization layer, and serves as a foundation for subsequent processing steps. This multi-functionality reduces the need for additional specialized structures, thereby limiting the increase in fabrication complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges the well isolation function with the existing dielectric layer structure used in FinFET fabrication. By combining these functions into a single integrated approach rather than adding separate isolation structures, the increase in fabrication complexity is minimized.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Substantially reduces leakage current by up to 2 orders of magnitude and improves latch-up trigger voltage by up to 10%, allowing for closer device spacing without latch-up incidents.

Implementation Method 1

forming a dielectric material between remaining portions of the fins and within the recess... substantially reduces leakage current

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS20260060051A1FinFET Circuit Devices With Well Isolation
Publication Date: 2026.02.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260060051A1 patent drawing
  • US20260060051A1 patent drawing
  • US20260060051A1 patent drawing

AI summary

A method includes receiving a structure that includes a substrate including a first well region having a first dopant type and a second well region having a second dopant type that is opposite to the first dopant type; and fins extending above the substrate. The method further includes forming a patterned etch mask on the structure, wherein the patterned etch mask provides an opening that is directly above a first fin of the fins, wherein the first fin is directly above the first well region. The method further includes etching the structure through the patterned etch mask, wherein the etching removes the first fin and forms a recess in the substrate that spans from the first well region into the second well region; and forming a dielectric material between remaining portions of the fins and within the recess.