FinFET Well Region Formation via Segmented Annealing
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Solution Overview
Problem
Existing semiconductor fabrication methods for FinFET structures face issues such as severe diffusion of P-type well regions during high-temperature water vapor thermal annealing, leading to punch-through and increased junction capacitances, which affect the electrical properties of the devices.
Innovation Solution
A method involving the formation of first and second well regions in the semiconductor substrate, where the second well regions are formed on the sides of the first well regions, and both are created after a first annealing process that converts an isolation flowable layer into an isolation film, preventing excessive diffusion and reducing the likelihood of punch-through issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature water vapor thermal annealing is performed to form isolation film, then the isolation film is successfully formed, but severe diffusion of P-type well ions occurs leading to punch-through
Solution Approach 1:
The patent segments the single high-temperature annealing process into multiple distinct steps: first forming the isolation film at high temperature, then performing low-temperature annealing to form well regions. This temporal and functional segmentation prevents P-type well ions from diffusing during the high-temperature isolation film formation, as the well regions are created afterward when diffusion is minimized by the lower temperature.
Solution Approach 2:
The patent performs preliminary action by forming the isolation film completely before creating the well regions. This sequence ensures that the isolation structure is established first, and subsequent well region formation occurs under controlled low-temperature conditions that prevent excessive ion diffusion and punch-through effects.
2Reliability
If high-temperature annealing is performed to form isolation film, then isolation film is formed, but junction capacitances increase
Solution Approach 1:
The patent divides the thermal processing into separate stages: high-temperature annealing exclusively for isolation film formation, followed by low-temperature annealing for well region creation. This segmentation ensures that junction formation occurs at lower temperatures, thereby controlling junction capacitances while still achieving complete isolation film formation in the earlier high-temperature step.
Solution Approach 2:
The patent changes the temperature parameter between process steps: using high temperature for isolation film formation, then reducing to low temperature for well region formation. This parameter change optimizes both isolation quality and junction characteristics by matching temperature conditions to specific process requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the electrical properties of semiconductor devices by minimizing the diffusion of well ions and reducing punch-through issues, thereby enhancing the performance of FinFET structures.
Implementation Method 1
performing a first annealing process to turn the isolation flowable layer into an isolation film
Data Source
AI summary
Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on a surface of the semiconductor substrate; forming an isolation flowable layer covering the plurality of fins over the semiconductor substrate; performing a first annealing process to turn the isolation flowable layer into an isolation film; and forming first well regions and second well regions in the fins and the semiconductor substrate. The second well regions are at two sides of the first well regions and contact with the first well regions; the first well regions have a first type of well ions; the second well regions have a second type of well ions; and the first type is opposite to the second type in the conductivities.