FinFET Metal Gate WFM Tuning for Threshold Voltage Control

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In the semiconductor industry, manufacturing self-aligned contact structures over source/drain regions in nanometer technology process nodes poses challenges due to the complexity of three-dimensional designs and the need for precise control of threshold voltages in Fin FETs and metal gate structures.

Innovation Solution

A method involving the sequential fabrication of fin structures, dummy gate formation, recessing, and metal gate structure creation, with the use of work function adjustment layers (WFM) to adjust threshold voltages by varying their thickness and materials, allowing for precise control of threshold voltages across different transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If work function adjustment layers with varying thickness and materials are used to adjust threshold voltages, then threshold voltage control precision is improved, but device structure complexity increases

Engineering Contradiction:
Improvethreshold voltage control precisionVSAvoiddevice structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by using different work function adjustment layer configurations for different transistor types. Specifically, first-type-channel transistors receive a first work function adjustment layer while second-type-channel transistors receive a second work function adjustment layer with different material composition or thickness. This localized differentiation enables precise threshold voltage control for each transistor type without unnecessarily complicating the entire device structure, as each region receives only the specific treatment it requires.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If multiple etching steps are performed to form self-aligned contact structures, then manufacturing precision is improved, but etching damage increases

Engineering Contradiction:
Improveself-aligned contact structure precisionVSAvoidetching damage
Core Design Contradiction:
Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by forming a protective layer on the gate structure before performing etching operations to create self-aligned contact structures. This protective layer is deposited in advance to shield the gate from etching damage, and is subsequently removed after the etching is complete. This preliminary protective measure enables the necessary multiple etching steps to achieve high precision self-aligned contact structures while minimizing harmful etching damage to the gate, as the gate is protected during the etching process.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12166038B2Semiconductor device and a method for fabricating the same
Publication Date: 2024.12.10 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12166038B2 patent drawing
  • US12166038B2 patent drawing
  • US12166038B2 patent drawing

AI summary

A semiconductor device includes first-type-channel field effect transistors (FETs) including a first first-type-channel FET including a first gate structure and a second first-type-channel FET including a second gate structure. The first first-type-channel FET has a smaller threshold voltage than the second first-type-channel FET. The first gate structure includes a first work function adjustment material (WFM) layer and the second gate structure includes a second WFM layer. At least one of thickness and material of the first and second WFM layers is different from each other.