Fin-FET Gate Work Function Layer Corner Thickening
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Solution Overview
Problem
Fin-FET devices face challenges in controlling the channel due to reduced channel length, leading to subthreshold leakage and short-channel effects (SCEs), which affect the gate's ability to pinch off the channel and impact electrical performance.
Innovation Solution
A method for fabricating Fin-FETs involving the formation of fin structures, an isolation layer, and interlayer dielectric layers, with a back-flow annealing process to thicken the N-type work function layer at corner regions and diffuse aluminum ions into the barrier layer, improving gate controllability and reducing barrier height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is reduced to increase transistor density and switching speed, then transistor density and switching speed are improved, but gate controllability deteriorates and subthreshold leakage increases
Solution Approach 1:
The patent transitions from planar MOSFET to Fin-FET structure, utilizing three-dimensional vertical fins to enhance gate controllability. The gate electrode wraps around the fin structure from multiple sides, providing superior electrostatic control over the channel despite reduced channel length, thereby suppressing subthreshold leakage while maintaining high transistor density
2Ease of manufacture
If conventional planar MOSFET structure is used, then manufacturing is simpler, but gate controllability is insufficient for scaled devices
Solution Approach 1:
The patent employs Fin-FET technology which introduces vertical dimension to the transistor structure. The fin structures extend vertically from the substrate, allowing the gate to control the channel from multiple surfaces. This three-dimensional architecture provides enhanced gate controllability for scaled devices while maintaining compatibility with existing semiconductor manufacturing processes
3Speed
If the channel length is reduced, then switching speed is improved, but subthreshold leakage phenomena increase
Solution Approach 1:
The Fin-FET structure with vertical fins enables the gate electrode to control the channel from at least two side surfaces simultaneously. This multi-surface control mechanism provides stronger electrostatic confinement of the channel, effectively suppressing subthreshold leakage currents even when the channel length is reduced to achieve faster switching speeds
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances gate controllability and extends the effective channel length, reducing SCEs and improving the electrical performance of Fin-FET devices by compensating for weak short-channel controllability and source-drain punch through issues.
Implementation Method 1
performing a back-flow annealing process on the N-type work function layer such that the N-type work function layer has a thickened portion at the corner region and a portion of the N-type work function layer at the corner region includes diffused aluminum ions
Data Source
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AI summary
A method for fabricating a Fin-FET includes forming a plurality of fin structures, an isolation layer, and an interlayer dielectric layer on an NMOS region of a substrate, forming a first opening in the interlayer dielectric layer to expose a portion of the fin structures. A region adjacent to a joint between a bottom surface and a sidewall surface of the first opening is a corner region. The method includes forming a high-k dielectric layer on the bottom and the sidewall surfaces of the first opening, a barrier layer on the high-k dielectric layer, and an N-type work function layer containing aluminum ions on the barrier layer. The method further includes performing a back-flow annealing process such that the portion of N-type work function layer at the corner region is thickened and contains diffused aluminum ions. Finally, the method includes forming a metal layer on the N-type work function layer.