FinFET Gate Work Function Layering for Threshold Voltage Tuning
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing advanced FinFET devices due to complexities in processing and patterning, particularly in achieving precise control over trench depths and isolation structures, which can lead to issues like etching penetration and varying threshold voltages across transistors.
Innovation Solution
The solution involves a multi-step process for forming FinFET devices, including the formation of trenches, dielectric material deposition, dummy gate structure creation, and work function metal layer formation, with specific techniques to prevent etching penetration and tune threshold voltages, such as using BARC layers and patterned masks to control etchant flow and work function metal layer thicknesses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography and self-aligned processes are used to pattern fins, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The method performs preliminary patterning actions by forming a mandrel structure first, then using it as a template for subsequent fin formation. The mandrel is prepared in advance with specific patterns that guide the self-aligned process, allowing precise fin positioning to be achieved through pre-planned pattern transfer rather than direct complex patterning
Solution Approach 2:
The patent introduces a mandrel structure as an intermediary element that mediates between the photolithography pattern and the final fin structure. The mandrel serves as a temporary template that simplifies the patterning process by providing a straightforward pattern transfer mechanism, reducing the direct complexity of fin patterning while maintaining precision
2Adaptability or versatility
If multiple work function metal layers are deposited, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent applies different work function metal materials to different regions of the gate structure. Specifically, a first work function metal is deposited in the first region while a second work function metal is deposited in the second region, allowing independent threshold voltage optimization for different transistor types (e.g., NFET and PFET) without requiring complex monolithic gate structures
Solution Approach 2:
The gate structure is segmented into multiple regions with different work function metal layers. This segmentation allows each region to be independently optimized for specific electrical characteristics, providing adaptability for different device requirements while maintaining a relatively simple overall deposition process through sequential layer formation
3Manufacturing precision
If epitaxy processes are used to form source/drain features, then manufacturing precision is improved, but loss of substance increases
Solution Approach 1:
The method performs preliminary formation of source/drain features through epitaxial growth before final device completion. The epitaxy process grows semiconductor material in advance to form precisely controlled source and drain regions with specific crystal orientations and compositions, enabling high manufacturing precision while allowing material to be grown only where needed rather than requiring extensive material removal
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the prevention of etching penetration and allows for the integration of transistors with different threshold voltages, enhancing device performance and manufacturing efficiency by maintaining precise control over trench structures and work function layers.
Implementation Method 1
This method enhances device performance by straining channels, improving carrier mobility
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a first semiconductor fin, a second semiconductor fin, an isolation structure, and a gate structure. The first and second semiconductor fins extend upwards from a top surface of the semiconductor substrate. The isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate structure includes a first work function layer, a second work function layer, and a third work function layer. The first work function layer surrounds the first semiconductor fin and the second semiconductor fin. The second work function layer surrounds the first semiconductor fin and is over the first work function layer. The third work function layer surrounds the first semiconductor fin and is over the second work function layer and the isolation structure. The first work function layer is in contact with the second work function layer and the third work function layer.