FinFET Work Function Metal Patterning via Sacrificial Mask
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in fabricating FinFET devices with precise control over the formation of semiconductor fins and gate structures, which affects the device's performance and efficiency due to limitations in current photolithography and etching processes.
Innovation Solution
A method for fabricating FinFET devices involves a series of steps including deposition and photolithography processes to form pad and mask layers, etching to create semiconductor fins, and subsequent formation of isolation dielectric, gate dielectric, and dummy gate structures, followed by replacement gate and work function metal layer formation, with the use of sacrificial and protective layers to ensure precise patterning and etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography and etching processes are used, then manufacturing simplicity is maintained, but manufacturing precision of fin and gate structures deteriorates
Solution Approach 1:
The fabrication process is divided into multiple distinct stages: forming pad and mask layers, etching semiconductor fins, creating isolation dielectric, forming gate dielectric and dummy gate structures, and subsequent replacement gate formation. Each stage uses specialized layers and processes optimized for that specific task, thereby achieving high manufacturing precision through systematic process segmentation.
Solution Approach 2:
Sacrificial layers are formed in advance before the actual gate structure fabrication. These preliminary sacrificial layers serve as placeholders that guide subsequent etching and deposition processes, enabling precise fin and gate structure formation while maintaining process control through pre-planned structural arrangements.
2Productivity
If geometry size is reduced for scaling, then productivity and cost efficiency improve, but manufacturing precision requirements increase
Solution Approach 1:
Different layers are assigned specific local functions optimized for their particular role: pad layers for structural support, mask layers for pattern definition, isolation dielectric for electrical separation, and work function metal layers for electrical characteristics. This local optimization enables precise control of fin structures at reduced geometries while maintaining overall manufacturing efficiency.
Solution Approach 2:
Multiple intermediary layers are introduced between the substrate and final gate structure, including pad layers, mask layers, isolation dielectric, and sacrificial layers. These intermediary elements mediate the complex transformations required for precise fin formation at scaled dimensions, enabling each process step to work within optimized parameter ranges that maintain both precision and productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the precise formation of FinFET devices with improved control over fin and gate structures, enhancing carrier mobility and device performance by allowing for strained epitaxial source/drain structures and optimized work function tuning.
Implementation Method 1
patterning the first work function metal layer using the sacrificial layer, resulting in a patterned work function metal layer under the sacrificial layer, and a work function metal residue in the vicinity of the second semiconductor fin
Implementation Method 2
selectively forming a protective layer on a side surface of the sacrificial layer and a side surface of the patterned first work function metal layer
Implementation Method 3
removing the work function metal residue after selectively forming the protective layer
Data Source
AI summary
A method includes forming a work function metal layer over first and second semiconductor fins extending upward from a substrate; forming a sacrificial layer straddling the first semiconductor fin but not overlapping the second semiconductor fin; patterning the first work function metal layer using the sacrificial layer, resulting in a patterned work function metal layer under the sacrificial layer, and a work function metal residue in the vicinity of the second semiconductor fin; selectively forming a protective layer on a side surface of the sacrificial layer and a side surface of the patterned first work function metal layer; removing the work function metal residue after selectively forming the protective layer; after removing the work function metal residue, removing the sacrificial layer and the protective layer; and forming a second work function metal layer over the first and second semiconductor fins.