FinFET Work Function Layer Layout for Multi-Vt Tuning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for forming transistors with multiple threshold voltages require stacking multiple work function layers, leading to increased total thickness and infeasibility in advanced technologies, and lack efficient methods for reducing the thickness of work function layers while achieving multiple threshold voltage levels.
Innovation Solution
The formation of Fin Field-Effect Transistors (FinFETs) involves depositing and patterning multiple work function layers with different work functions, using one layer as an etch stop to limit the total thickness of work function layers, and skipping capping and barrier layers to reduce gate stack thickness, allowing for the achievement of multiple threshold voltage levels with fewer layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple work function layers are stacked to achieve multiple threshold voltage levels, then the threshold voltage tuning capability is improved, but the total thickness of work function layers increases making the process infeasible in advanced technologies
Solution Approach 1:
The patent segments the work function layers into distinct layers with different work functions (first work function layer and second work function layer), where each layer contributes to different threshold voltage levels. This segmentation allows achieving multiple threshold voltage levels without requiring excessive total thickness, as each segment serves a specific function in the threshold voltage tuning hierarchy.
Solution Approach 2:
The patent applies local quality by assigning different work function characteristics to different layers (first work function layer with first work function, second work function layer with second work function). This allows different regions of the gate stack to have optimized local properties for achieving multiple threshold voltage levels while controlling overall thickness.
2Adaptability or versatility
If conventional formation methods are used with multiple stacked work function layers, then multiple threshold voltage levels can be achieved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The gate stack is segmented into functional layers (high-k gate dielectric layer, first work function layer, second work function layer, capping layer) where each segment has a specific role. This functional segmentation simplifies the manufacturing process by allowing selective formation and removal of specific layers to achieve different threshold voltage levels, reducing overall device complexity.
Solution Approach 2:
The patent changes the work function parameter of different layers to achieve multiple threshold voltage levels. By selecting materials with different work functions for the first and second work function layers, the patent achieves threshold voltage tuning through parameter variation rather than through complex structural arrangements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of transistors with different threshold voltages while maintaining a limited total thickness of work function layers, overcoming the limitations of conventional methods by allowing for more advanced transistor designs.
Implementation Method 1
depositing a high-k gate dielectric and metal layers over the high-k gate dielectric
Implementation Method 2
depositing a high-k gate dielectric and metal layers over the high-k gate dielectric
Implementation Method 3
performing Chemical Mechanical Polish (CMP) to remove excess portions of the high-k gate dielectric and the metal layers
Implementation Method 4
depositing and patterning multiple work function layers with different work functions
Data Source
AI summary
A structure includes a semiconductor substrate including a first semiconductor region and a second semiconductor region, a first transistor in the first semiconductor region, and a second transistor in the second semiconductor region. The first transistor includes a first gate dielectric over the first semiconductor region, a first work function layer over and contacting the first gate dielectric, and a first conductive region over the first work function layer. The second transistor includes a second gate dielectric over the second semiconductor region, a second work function layer over and contacting the second gate dielectric, wherein the first work function layer and the second work function layer have different work functions, and a second conductive region over the second work function layer.