FinFET Recess Depth Control for SRAM Current Optimization

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Solution Overview

Problem

In FinFET technology, the transition from continuous to discrete fin widths complicates the optimization of current fabrication processes, particularly for SRAM and analog or mixed signal designers, making it challenging to achieve specific on-current values.

Innovation Solution

A method involving the formation of substrates with different recess depths on various regions, followed by the creation of metal gates, allows for the adjustment of fin heights and depths to optimize transistor performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If discrete fin widths are used in FinFET structures, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvefin width controlVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The substrate is divided into multiple regions with different recess depths, allowing discrete fin widths to be formed in different areas. This segmentation enables precise control of fin dimensions while maintaining a systematic fabrication approach that doesn't overly complicate the overall process.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If multiple regions with different fin heights are created, then adaptability is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvedesign flexibilityVSAvoidrecess depth control
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

Different regions of the substrate are given different recess depths to create locally optimized fin structures. This local quality approach allows each region to have tailored fin heights suited for specific circuit requirements, enhancing design flexibility while using standard fabrication techniques to maintain manufacturing precision.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20180122705A1Method for fabricating semiconductor device
Publication Date: 2018.05.03 UNITED MICROELECTRONICS CORP
  • US20180122705A1 patent drawing
  • US20180122705A1 patent drawing
  • US20180122705A1 patent drawing

AI summary

First, a substrate having a first region and a second region is provided, a first gate structure is formed on the first region and a second gate structure is formed on the second region, an interlayer dielectric (ILD) layer is formed around the first gate structure and the second gate structure, and the first gate structure and the second gate structure are removed to expose the substrate on the first region and the second region. Next, part of the substrate on the first region is removed to form a first recess and part of the substrate on the second region is removed to form a second recess, in which the depths of the first recess and the second recess are different. Next, a first metal gate is formed on the first region and a second metal gate is formed on the second region.