Finger Capacitor Cell Segmentation for Parasitic Resistance Reduction
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Solution Overview
Problem
As semiconductor device fabrication nodes shrink, the quality factor of finger capacitors in integrated circuits degrades due to metal routing restrictions, metal coloring requirements, and increased metal resistances, making it challenging to achieve high performance, especially at higher frequencies.
Innovation Solution
The use of a plurality of cells in a finger capacitor design, where cells are connected using wider buses and additional metal layers to reduce parasitic resistance and improve the quality factor, while maintaining or reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional finger capacitor designs are used in smaller fabrication nodes, then device density increases, but quality factor degrades due to metal routing restrictions and increased metal resistance
Solution Approach 1:
The capacitor is divided into multiple cells arranged in a grid pattern, with each cell containing interdigitated finger structures. This segmentation allows the use of wider bus structures connecting the cells, which reduces parasitic resistance while maintaining high device density through efficient space utilization
Solution Approach 2:
The invention transitions from conventional two-dimensional finger arrangements to a three-dimensional multi-layer structure with cells distributed across different metal layers. This dimensional expansion allows for wider inter-cell bus connections that reduce parasitic resistance while maintaining compact footprint
2Ease of manufacture
If metal routing restrictions and metal coloring requirements are imposed, then fabrication compliance is achieved, but parasitic resistance increases and quality factor deteriorates
Solution Approach 1:
Different regions of the capacitor structure are optimized with different properties: the finger structures within cells use minimum width to maximize capacitance density, while the inter-cell bus structures use wider widths to minimize parasitic resistance. This local quality differentiation allows compliance with metal routing restrictions while maintaining high quality factor
3Reliability
If wider buses are used to connect cells, then parasitic resistance decreases and quality factor improves, but parasitic capacitance may increase
Solution Approach 1:
The invention introduces carefully designed bus structures that act as intermediaries between the finger structures of adjacent cells. These buses are optimized with specific width and spacing parameters to provide low-resistance connections while minimizing parasitic capacitance through controlled geometry and dielectric material selection
Data Source
AI summary
A capacitor includes a first metal layer over a substrate, a second metal layer over the first metal layer, and first and second cells. Each cell is electrically coupled to first and second buses. Each cell includes first plurality and second plurality of fingers in the first metal layer, and third plurality and fourth plurality of fingers in the second metal layer. The first plurality of fingers extend in a first direction parallel to a top surface of the substrate and are electrically coupled to the first bus. The second plurality of fingers extend in the first direction and are electrically coupled to the second bus. The third plurality of fingers extend in a second direction parallel to the top surface of the substrate and are electrically coupled to the first bus. The second direction is different from the first direction. The fourth plurality of fingers extend in the second direction and are electrically coupled to the second bus.