Finger Capacitor Array Layout for Low-Parasitic Compact ICs
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Solution Overview
Problem
Conventional semiconductor capacitor arrays face issues with parasitic capacitance and wastage of circuit area due to the design of capacitor units, especially when adapted for advanced processes like FinFET.
Innovation Solution
The finger-type semiconductor capacitor array layout incorporates a first conductive structure with longitudinal first conductive strips and lateral power supply strips, and a second conductive structure with longitudinal second conductive strips and lateral power supply strips, arranged to minimize parasitic capacitance and optimize circuit area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the gap between the first capacitor row and the second capacitor row is broadened to avoid parasitic capacitance, then the accuracy of capacitance is improved, but the circuit area is wasted
Solution Approach 1:
The patent transitions from a planar parallel arrangement to a three-dimensional stacked arrangement of capacitor rows. The first and second capacitor rows are positioned in different metal layers (first metal layer and second metal layer respectively), utilizing the vertical dimension to separate capacitor elements that would otherwise need lateral separation. This dimensional change allows capacitor rows to be closely spaced horizontally while maintaining electrical isolation through vertical stacking and insulating structures.
Solution Approach 2:
The patent implements nested positioning where the first capacitor row and second capacitor row are interleaved in an alternating pattern across multiple metal layers. The insulating structures are positioned between and around the capacitor rows, creating a nested configuration where insulating elements are embedded within the capacitor array structure. This nesting allows maximum utilization of available space while maintaining required isolation.
2Ease of manufacture
If the ratio (W/L) of the U-shaped structure is enlarged to conform to advanced process specifications, then the manufacturing compliance is improved, but the circuit area consumption increases
Solution Approach 1:
The patent segments the capacitor structure into multiple independent capacitor units arranged in series and parallel configurations across different metal layers. Instead of using large U-shaped structures, the capacitance is achieved through multiple smaller capacitor elements (first capacitor rows and second capacitor rows) that are distributed across the available area. This segmentation allows each element to meet minimum dimension requirements for advanced processes while the overall capacitance is achieved through the combined effect of multiple elements.
Solution Approach 2:
The patent utilizes the vertical dimension by stacking capacitor rows across multiple metal layers to achieve the required capacitance values without enlarging the lateral dimensions of individual capacitor elements. The W/L ratio constraints are satisfied by using multiple layers rather than increasing the size of single-plane structures, thereby maintaining compact circuit area while conforming to advanced process specifications.
Data Source
AI summary
A finger-type semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes longitudinal first conductive strips and lateral power supply strips. The second conductive structure includes longitudinal second conductive strips and P lateral power supply strip(s). The longitudinal first conductive strips and the longitudinal second conductive strips are alternately disposed in a first integrated circuit (IC) layer; and the longitudinal first conductive strips include a first row of strips and a second row of strips. The lateral power supply strips are located in a second IC layer, and coupled to the first and second rows of strips through vias. The P lateral power supply strip(s) is/are located in the second IC layer, and include(s) a first-capacitor-group power supply strip that is coupled to K strip(s) of the longitudinal second conductive strips through K via(s). The P and K are positive integers.