Finger-Shaped Insulation Structure for High-Voltage MOS Transistors
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Solution Overview
Problem
Conventional high-voltage MOS transistor devices occupy valuable chip space and have high drain-source-on-state resistance, making it difficult to enhance breakdown voltage and reduce device size effectively.
Innovation Solution
A high-voltage semiconductor device with a conductive structure embedded in an insulation unit between the gate structure and the drain, allowing for controlled electrical potential to improve breakdown voltage and reduce drain-source-on-state resistance without increasing device area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high-voltage MOS transistor structures (such as LDMOS, DDDMOS, FDMOS, or DEMOS) are used to enhance breakdown voltage, then the device area increases, but the valuable chip space is occupied and drain-source-on-state resistance increases
Solution Approach 1:
The conductive structure is embedded within the insulation unit, creating a nested configuration where one structure is placed inside another. This allows the device to achieve high-voltage breakdown enhancement without proportionally increasing the overall device area, as the conductive elements are housed within the existing insulation space rather than requiring additional lateral expansion
Solution Approach 2:
The invention transitions from conventional lateral field management to vertical field management by embedding conductive structures within the insulation unit. This vertical arrangement allows for enhanced breakdown voltage through controlled electrical potential in the vertical dimension, while maintaining a compact lateral footprint that preserves chip space
2Reliability
If conventional high-voltage MOS transistor structures are used to enhance breakdown voltage, then the device area increases, but the drain-source-on-state resistance increases
Solution Approach 1:
The conductive structure is embedded within the insulation unit, creating a nested configuration where one structure is placed inside another. This allows the device to achieve high-voltage breakdown enhancement without proportionally increasing the overall device area, as the conductive elements are housed within the existing insulation space rather than requiring additional lateral expansion
Solution Approach 2:
The invention transitions from conventional lateral field management to vertical field management by embedding conductive structures within the insulation unit. This vertical arrangement allows for enhanced breakdown voltage through controlled electrical potential in the vertical dimension, while maintaining a compact lateral footprint that preserves chip space
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances electrical characteristics of high-voltage semiconductor devices, enabling improved breakdown voltage and reduced resistance without increasing device size, suitable for advanced process nodes like the 28 nm node and beyond.
Implementation Method 1
By controlling the electrical potential of the conductive structure embedded in the insulation unit, the breakdown voltage of the high-voltage semiconductor device may be improved, and the drain-source-on-state resistance of the high-voltage semiconductor device may be reduced accordingly
Data Source
AI summary
A high-voltage semiconductor device includes a semiconductor substrate, a gate structure, a drain, an insulation structure, and a plurality of conductive structures. The insulation structure is disposed in the semiconductor substrate and disposed between the gate structure and the drain. The insulation structure includes a plurality of insulation units disposed separately from one another. Each of the conductive structures is embedded in one of the insulation units.