Fingerprint-Sensing Display Panel Layout With Overlapping Control Lines
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Solution Overview
Problem
Existing display devices face challenges in achieving improved resolution and efficient integration of fingerprint sensing capabilities while optimizing the layout and overlap of control lines with transistors and capacitors in a display panel.
Innovation Solution
The display device incorporates a pixel circuit with a first transistor and capacitor, a sensor circuit with light receiving elements and switching transistors, and control lines that overlap with these components, with specific configurations to enhance resolution and sensor functionality, including overlapping control lines with capacitors and transistors in a plan view and minimizing insulating layers in cross-section.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If control lines are routed to overlap with transistors and capacitors in a plan view, then the area occupied by control lines is reduced and resolution is improved, but the complexity of layout design increases and signal interference may occur
Solution Approach 1:
The patent utilizes the third dimension (vertical stacking) by forming control lines, transistors, and capacitors in different layers. Specifically, control lines are positioned in conductive layers at different heights, with insulating layers separating them from transistors and capacitors. This vertical arrangement allows planar overlap without physical interference, achieving high resolution while managing layout complexity through 3D spatial organization.
2Device complexity
If control lines overlap with capacitors and transistors, then the number of insulating layers is reduced and device structure is simplified, but electrical interference and signal noise may increase
Solution Approach 1:
The patent introduces insulating layers as intermediary elements between control lines and active components (transistors and capacitors). These insulating layers act as mediators that allow the control lines to be positioned in close proximity to reduce the number of insulating layers needed, while simultaneously providing electrical isolation to prevent signal interference and maintain signal integrity.
3Reliability
If more insulating layers are added to separate control lines from transistors and capacitors, then electrical interference is reduced, but the device structure becomes more complex and manufacturing difficulty increases
Solution Approach 1:
The patent applies insulating layers selectively and locally rather than uniformly throughout the device. Insulating layers are positioned specifically at locations where control lines overlap with transistors or capacitors in the plan view, providing electrical isolation only where needed. This localized approach maintains reliable electrical isolation while minimizing the overall number of insulating layers and simplifying manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves display resolution and enables efficient fingerprint sensing by optimizing the layout of control lines and transistors, enhancing the overall performance of the display device.
Implementation Method 1
a sensor including a sensor circuit, light receiving elements, and switching transistors connecting the light receiving elements to the sensor circuit
Data Source
AI summary
A display device includes a pixel including a pixel circuit and a light emitting element connected to the pixel circuit, the pixel circuit including a first transistor and a capacitor; a sensor including a sensor circuit, light receiving elements, and switching transistors connecting the light receiving elements to the sensor circuit, the sensor circuit including a sensor transistor; and control lines configured to control operations of the switching transistors, at least one of the control lines overlapping with at least one of the first transistor and the capacitor in a plan view.