Fingerprint Identification Element Wiring Simplification

The patent transitions from a planar arrangement of photosensitive transistors to a three-dimensional stacked structure where multiple transistor layers are vertically integrated. This dimensional change allows signal lines to be routed through different layers and spatial positions, reducing planar wiring complexity while maintaining the necessary number of photosensitive elements for accurate fingerprint recognition

The patent implements shared signal lines that serve multiple photosensitive transistors across different layers and positions. The signal lines are designed to collect signals from multiple transistors simultaneously, reducing the total number of required signal lines while maintaining the ability to distinguish fingerprint valleys and ridges through coordinated transistor operation

The patent utilizes vertical stacking of transistor layers with signal lines routed through different spatial levels. This three-dimensional wiring architecture reduces the density of interconnections in any single plane, making the overall wiring structure more manageable and less complex despite the large number of required connections

The patent combines multiple signal collection functions into shared signal lines that traverse multiple layers and serve multiple photosensitive transistors. By merging these functions into unified signal pathways, the total number of distinct wiring routes is reduced, simplifying the overall wiring complexity while maintaining comprehensive signal collection capability